Patents by Inventor Wan Jun
Wan Jun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11983415Abstract: A memory management method for a memory storage device is provided. The memory management method includes: detecting effective information of at least one operation event performed by the memory storage device in a first mode; and adjusting a threshold value according to the effective information. The threshold value is configured to determine whether to instruct the memory storage device to enter the first mode.Type: GrantFiled: August 29, 2019Date of Patent: May 14, 2024Assignee: Hefei Core Storage Electronic LimitedInventors: Qi-Ao Zhu, Chong Peng, Zhi Wang, Wan-Jun Hong
-
Patent number: 11975037Abstract: The present specification relates to a composition for preventing, alleviating or treating burnout syndrome, containing a natural extract as an active ingredient. According to one aspect of the present invention, the composition contains a ginseng fruit extract, and thus is useful for preventing, treating and alleviating burnout syndrome. In addition, according to one aspect of the present invention, the composition further contains ginseng fruit and one or more selected from the group consisting of red ginseng, Angelica gigas, Cornus officinalis, Cervi parvum corni, and Nigella sativa, so as to maximize the synergistic effect among two or more ingredients, thereby exhibiting excellent effects on the prevention, treatment and alleviation of burnout syndrome. Therefore, there is an advantage of making individuals and society mentally and physically healthy since burnout syndrome can be prevented, treated and alleviated, by using the composition of the present invention.Type: GrantFiled: February 5, 2016Date of Patent: May 7, 2024Assignee: AMOREPACIFIC CORPORATIONInventors: Su-Hwan Kim, Chan-Woong Park, Sun Mi Kim, Juewon Kim, Byung Gyu Kim, Wan Gi Kim, Sang Jun Lee
-
Publication number: 20240128219Abstract: A semiconductor die including mechanical-stress-resistant bump structures is provided. The semiconductor die includes dielectric material layers embedding metal interconnect structures, a connection pad-and-via structure, and a bump structure including a bump via portion and a bonding bump portion. The entirety of a bottom surface of the bump via portion is located within an area of a horizontal top surface of a pad portion of the connection pad-and-via structure.Type: ApplicationFiled: December 6, 2023Publication date: April 18, 2024Inventors: Hui-Min Huang, Wei-Hung Lin, Kai Jun Zhan, Chang-Jung Hsueh, Wan-Yu Chiang, Ming-Da Cheng
-
Patent number: 11949012Abstract: A semiconductor device including: a first transistor which include a first gate stack on a substrate; and a second transistor which includes a second gate stack on the substrate, wherein the first gate stack includes a first ferroelectric material layer disposed on the substrate, a first work function layer disposed on the first ferroelectric material layer and a first upper gate electrode disposed on the first work function layer, wherein the second gate stack includes a second ferroelectric material layer disposed on the substrate, a second work function layer disposed on the second ferroelectric material layer and a second upper gate electrode disposed on the second work function layer, wherein the first work function layer includes the same material as the second work function layer, and wherein an effective work function of the first gate stack is different from an effective work function of the second gate stack.Type: GrantFiled: December 8, 2020Date of Patent: April 2, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jong Ho Park, Wan Don Kim, Weon Hong Kim, Hyeon Jun Baek, Byoung Hoon Lee, Jeong Hyuk Yim, Sang Jin Hyun
-
Publication number: 20240100911Abstract: A heat pump system includes a cooling apparatus in which a coolant is circulated, a compressor to compress a refrigerant, a condenser connected to the compressor through a refrigerant line and configured to condense the refrigerant by heat-exchanging with the refrigerant and the coolant, an evaporator connected to the condenser through the refrigerant line and configured to evaporate the refrigerant by heat-exchanging with the refrigerant and the coolant, a gas injection device provided in the refrigerant line between the condenser and the evaporator and configured to selectively expand and flow the refrigerant and selectively supply some of the refrigerant to the compressor, a refrigerant connection line including a first end connected to the refrigerant line and a second end connected to the gas injection device between the compressor and the evaporator, and a chiller in the refrigerant connection line for adjusting a temperature of the coolant by heat-exchange.Type: ApplicationFiled: February 9, 2023Publication date: March 28, 2024Inventors: Jeawan Kim, Hochan An, Wan Je Cho, Hoyoung Jeong, Man Hee Park, Yeong Jun Kim, Jae Yeon Kim, Yeonho Kim
-
Publication number: 20240075060Abstract: The present invention relates to an oral solid formulation for colon cleansing, wherein the oral solid formulation minimizes side effects, has excellent dosing convenience and medication compliance, enables a pharmaceutical effect to be exhibited quickly, and has excellent colon cleansing ability.Type: ApplicationFiled: December 30, 2021Publication date: March 7, 2024Applicant: TAEJOON PHARMACEUTICAL CO., LTD.Inventors: Joon Youb LEE, Wan GU, Woo Young JANG, Young Un KIM, Yong Jun KIM
-
Publication number: 20240075028Abstract: Provided is a pharmaceutical composition comprising as active ingredients: 5 mg of tadalafil or a pharmaceutically acceptable salt thereof; and 0.5 mg of dutasteride or a pharmaceutically acceptable salt thereof, wherein the dissolution rate of tadalafil under the dissolution conditions of a paddle rate of 50 rpm in 500 mL of a dissolution solution having a pH of 1.2 and containing 0.25% of SLS is 60-75% after 5 minutes and 80% or more after 30 minutes, and the dissolution rate of dutasteride under the dissolution conditions of a paddle rate of 50 rpm in 500 mL of a dissolution solution containing water and 0.1% of SLS is 50% or more after 15 minutes and 85% or more after 30 minutes.Type: ApplicationFiled: December 30, 2021Publication date: March 7, 2024Inventors: Ye Ri LEE, Sung Hoon JUN, Jong Sil KIM, Kye Wan LEE
-
Patent number: 11803331Abstract: A memory management method, a memory storage device and a memory control circuit unit are disclosed. The method includes: performing a first write operation to store first data to a first physical unit; recording first unit management information corresponding to the first write operation, wherein the first unit management information reflects a usage order of first used physical units, and the first used physical units include the first physical unit; performing data merge operation to copy at least a part of data stored in the first physical unit to a second physical unit; and after the data merge operation is performed, recording second unit management information according to the first unit management information, wherein the second unit management information reflects a usage order of second used physical units. The second used physical units include the second physical unit but do not include the first physical unit.Type: GrantFiled: December 29, 2021Date of Patent: October 31, 2023Assignee: Hefei Core Storage Electronic LimitedInventors: Wan-Jun Hong, Yang Zhang, Wenbin Tao, Hao Yang, Mengkai Wu, Yankai Dai
-
Publication number: 20230205451Abstract: A multi-channel memory storage device, a memory control circuit unit, and a data reading method are provided. The method includes: determining whether a storage space of a buffer memory is insufficient when a multi-channel access is performed; issuing a data read command corresponding to each of a plurality of multi-channels to a rewritable non-volatile memory module according to a logical address in a host read command in response to insufficient storage space of the buffer memory to read data corresponding to each of the plurality of multi-channels from a data storage area to a data cache area via the plurality of multi-channels; and allocating the storage space of the buffer memory to the rewritable non-volatile memory module after the storage space of the buffer memory is released and issuing a cache read command to move first data in data temporarily stored in the data cache area to the buffer memory.Type: ApplicationFiled: January 19, 2022Publication date: June 29, 2023Applicant: Hefei Core Storage Electronic LimitedInventors: Wan-Jun Hong, Qi-Ao Zhu, Xin Wang, Yang Zhang, Xu Hui Cheng, Jian Hu
-
Publication number: 20230176782Abstract: A memory management method, a memory storage device and a memory control circuit unit are disclosed. The method includes: performing a first write operation to store first data to a first physical unit; recording first unit management information corresponding to the first write operation, wherein the first unit management information reflects a usage order of first used physical units, and the first used physical units include the first physical unit; performing data merge operation to copy at least a part of data stored in the first physical unit to a second physical unit; and after the data merge operation is performed, recording second unit management information according to the first unit management information, wherein the second unit management information reflects a usage order of second used physical units. The second used physical units include the second physical unit but do not include the first physical unit.Type: ApplicationFiled: December 29, 2021Publication date: June 8, 2023Applicant: Hefei Core Storage Electronic LimitedInventors: Wan-Jun Hong, Yang Zhang, Wenbin Tao, Hao Yang, Mengkai Wu, Yankai Dai
-
Patent number: 11669270Abstract: A multi-channel memory storage device, a memory control circuit unit, and a data reading method are provided. The method includes: determining whether a storage space of a buffer memory is insufficient when a multi-channel access is performed; issuing a data read command corresponding to each of a plurality of multi-channels to a rewritable non-volatile memory module according to a logical address in a host read command in response to insufficient storage space of the buffer memory to read data corresponding to each of the plurality of multi-channels from a data storage area to a data cache area via the plurality of multi-channels; and allocating the storage space of the buffer memory to the rewritable non-volatile memory module after the storage space of the buffer memory is released and issuing a cache read command to move first data in data temporarily stored in the data cache area to the buffer memory.Type: GrantFiled: January 19, 2022Date of Patent: June 6, 2023Assignee: Hefei Core Storage Electronic LimitedInventors: Wan-Jun Hong, Qi-Ao Zhu, Xin Wang, Yang Zhang, Xu Hui Cheng, Jian Hu
-
Publication number: 20230094144Abstract: A memory system may improve the endurance and performance of a plurality of memories included in the memory system mounted on a server system or a data processing system. For example, the memory system may throttle energy of a first memory using a second memory having a different characteristic from the first memory, control accesses to a memory region according to a refresh cycle, and control accesses to memories having different temperatures according to a priority of a request for each of the memories.Type: ApplicationFiled: November 30, 2022Publication date: March 30, 2023Inventors: Wan-Jun Roh, Hyun-Sup Kim, Hyung-Sik Won
-
Publication number: 20230098366Abstract: A memory polling method, a memory storage device and a memory control circuit unit are provided. The memory polling method includes: detecting a plurality of busy times corresponding to a plurality of physical units when executing a plurality of first commands; counting the busy times corresponding to the physical units to generate a count statistic value, and determine a delay time based on the count statistic value; and transmitting a plurality of status requests to a rewritable non-volatile memory module after the delay time.Type: ApplicationFiled: October 13, 2021Publication date: March 30, 2023Applicant: Hefei Core Storage Electronic LimitedInventors: Qi-Ao Zhu, Jing Zhang, Kuai Cao, Xin Wang, Xu Hui Cheng, Wan-Jun Hong
-
Patent number: 11544168Abstract: A memory system may improve the endurance and performance of a plurality of memories included in the memory system mounted on a server system or a data processing system. For example, the memory system may throttle energy of a first memory using a second memory having a different characteristic from the first memory, control accesses to a memory region according to a refresh cycle, and control accesses to memories having different temperatures according to a priority of a request for each of the memories.Type: GrantFiled: April 24, 2020Date of Patent: January 3, 2023Assignee: SK hynix Inc.Inventors: Wan-Jun Roh, Hyung-Sup Kim, Hyung-Sik Won
-
Patent number: 11487661Abstract: A converged memory device includes: a first memory group having first characteristics; a second memory group having second characteristics that are different from the first characteristics; and a controller configured to migrate predetermined data of the second memory group into a cache region in the first memory group, wherein the controller is further configured to migrate data of the second memory group into the cache region by using the cache region as a buffer when an energy throttling operation is performed on the second memory group.Type: GrantFiled: September 15, 2020Date of Patent: November 1, 2022Assignee: SK hynix Inc.Inventor: Wan-Jun Roh
-
Patent number: 11483505Abstract: In accordance with an embodiment of the present disclosure, an image synchronization device includes a light emitting source configured to emit light at intervals of a predetermined time, a sampling phase calibration circuit configured to calibrate a sampling phase of each of the first image sensor and the second image sensor on the basis of a light emitting timing of the light emitting source and a delay calibration circuit configured to generate delay information on the basis of a result of comparison between first image information transmitted from the first image sensor and second image information transmitted from the second image sensor.Type: GrantFiled: June 14, 2018Date of Patent: October 25, 2022Assignee: SK hynix Inc.Inventors: Chang Hyun Kim, Wan Jun Roh, Doo Bock Lee, Seung Hun Lee, Jae Jin Lee, Chun Seok Jeong
-
Patent number: 11281402Abstract: A memory management method. The memory management method includes: receiving a command from a host system; sending a command sequence corresponding to the command to a rewritable non-volatile memory module; determining a delay time; and sending a plurality of polling commands to the rewritable non-volatile memory module after the delay time.Type: GrantFiled: January 22, 2020Date of Patent: March 22, 2022Assignee: Hefei Core Storage Electronic LimitedInventors: Qi-Ao Zhu, Jing Zhang, Wan-Jun Hong, Ya-Lin Zhu, Tong-Jin Liu
-
Publication number: 20210377483Abstract: In accordance with an embodiment of the present disclosure, an image synchronization device includes a light emitting source configured to emit light at intervals of a predetermined time, a sampling phase calibration circuit configured to calibrate a sampling phase of each of the first image sensor and the second image sensor on the basis of a light emitting timing of the light emitting source and a delay calibration circuit configured to generate delay information on the basis of a result of comparison between first image information transmitted from the first image sensor and second image information transmitted from the second image sensor.Type: ApplicationFiled: June 14, 2018Publication date: December 2, 2021Inventors: Chang Hyun KIM, Wan Jun ROH, Doo Bock LEE, Seung Hun LEE, Jae Jin LEE, Chun Seok JEONG
-
Patent number: 11175847Abstract: A data merging method for flash memory, a flash memory control circuit unit and a flash memory storage device are provided. The disclosure is applicable to a flash memory, an embedded memory device or a solid state drive of 3D structure. The method includes: selecting at least one source physical erasing unit from at least one first physical erasing unit according to a valid data count of the at least one first physical erasing unit and a valid data count of each of a plurality of memory sub-modules; and copying valid data in the at least one source physical erasing unit to at least one destination physical erasing unit to perform a valid data merging operation.Type: GrantFiled: March 18, 2020Date of Patent: November 16, 2021Assignee: Hefei Core Storage Electronic LimitedInventors: Qi-Ao Zhu, Wan-Jun Hong, Jing Zhang, Xin Wang, Xu Hui Cheng
-
Publication number: 20210223976Abstract: A data merging method for flash memory, a flash memory control circuit unit and a flash memory storage device are provided. The disclosure is applicable to a flash memory, an embedded memory device or a solid state drive of 3D structure. The method includes: selecting at least one source physical erasing unit from at least one first physical erasing unit according to a valid data count of the at least one first physical erasing unit and a valid data count of each of a plurality of memory sub-modules; and copying valid data in the at least one source physical erasing unit to at least one destination physical erasing unit to perform a valid data merging operation.Type: ApplicationFiled: March 18, 2020Publication date: July 22, 2021Applicant: Hefei Core Storage Electronic LimitedInventors: Qi-Ao Zhu, Wan-Jun Hong, Jing Zhang, Xin Wang, Xu Hui Cheng