Patents by Inventor Wang-Chun Huang
Wang-Chun Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240178052Abstract: A semiconductor structure includes a substrate, a first gate structure and a second gate structure disposed over the substrate, and an isolation feature extending through the substrate and disposed between the first gate structure and the second gate structure. A top surface of the isolation feature is above a topmost surface of the first gate structure.Type: ApplicationFiled: February 5, 2024Publication date: May 30, 2024Inventors: Wang-Chun HUANG, Yu-Xuan HUANG, Hou-Yu CHEN, Chih-Hao WANG, Kuan-Lun CHENG
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Patent number: 11973077Abstract: A device includes a transistor, a backside via, and a pair of sidewall spacers. The transistor includes a gate structure, a channel layer surrounded by the gate structure, and a first source/drain structure and a second source/drain structure connected to the channel layer. The backside via is under and connected to the first source/drain structure and includes a first portion, a second portion between the first portion and the first source/drain structure, and a third portion tapering from the first portion to the second portion in a cross-sectional view. The pair of sidewall spacers are on opposite sidewalls of the second portion of the backside via but not on opposite sidewalls of the first portion of the backside via.Type: GrantFiled: April 21, 2023Date of Patent: April 30, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wang-Chun Huang, Hou-Yu Chen, Kuan-Lun Cheng, Chih-Hao Wang
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Publication number: 20240096979Abstract: A method for forming a semiconductor structure is provided. The method includes forming a fin structure protruding from a substrate. The fin structure includes alternately stacked first semiconductor material layers and second semiconductor material layers. The method includes forming a spacer layer over the fin structure. The method includes forming a first inter-layer dielectric (ILD) layer over the spacer layer. The method also includes recessing the fin structure and the first ILD layer to form a first opening through the first ILD layer. The method further includes forming an epitaxial structure in the first opening, and forming a second ILD layer over the epitaxial structure and the first ILD layer. In addition, the method includes removing the first semiconductor material layers, and forming a gate structure around the second semiconductor material layers.Type: ApplicationFiled: January 11, 2023Publication date: March 21, 2024Inventor: Wang-Chun HUANG
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Publication number: 20240079277Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a substrate, an isolation layer, a gate stack structure, and a dielectric layer. The method includes partially removing the gate stack structure to form a first trench in the gate stack structure. The method includes forming an isolation structure in the first trench. The method includes removing the first gate stack and the second gate stack to form a first recess and a second recess in the dielectric layer. The method includes forming an n-type gate stack and a p-type gate stack in the first recess and the second recess respectively. The method includes forming a conductive line over the n-type gate stack, the p-type gate stack, and the isolation structure. The conductive line electrically connects the n-type gate stack to the p-type gate stack.Type: ApplicationFiled: January 10, 2023Publication date: March 7, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wang-Chun HUANG, Pei-Yu WANG
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Patent number: 11901365Abstract: A finFET device that includes a substrate and at least one semiconductor fin extending from the substrate. The fin may include a plurality of wide portions comprising a first semiconductor material and one or more narrow portions. The one or more narrow portions have a second width less than the first width of the wide portions. Each of the one or more narrow portions separates two of the plurality of wide portions from one another such that the plurality of wide portions and the one or more narrow portions are arranged alternatingly in a substantially vertical direction that is substantially perpendicular with a surface of the substrate. The fin may also include a channel layer covering sidewalls of the plurality of wide portions and a sidewall of the one or more narrow portions.Type: GrantFiled: May 4, 2021Date of Patent: February 13, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wang-Chun Huang, Kai-Chieh Yang, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang
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Patent number: 11894260Abstract: A semiconductor structure includes a gate structure surrounding a plurality of channels and a cut feature that electrically isolates two separate portions of the gate structure. The cut feature comprises an outer layer having a work-function metal, and an inner layer comprising a dielectric material. The cut feature extends above a top surface of the gate structure.Type: GrantFiled: August 9, 2022Date of Patent: February 6, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTDInventors: Wang-Chun Huang, Yu-Xuan Huang, Hou-Yu Chen, Kuan-Lun Cheng, Chih-Hao Wang
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Publication number: 20230387261Abstract: A semiconductor device includes semiconductor nanosheets, a gate structure, and a dielectric spacer. The semiconductor nanosheets are vertically stacked over each other, disposed above a semiconductor substrate, and serve as channel regions. A bottommost semiconductor nanosheet most proximate from the semiconductor substrate is a thinnest nanosheet of the semiconductor nanosheets. The gate structure surrounds each of the semiconductor nanosheets in a first cross-section, and the dielectric spacer is interposed between the bottommost semiconductor nanosheet and the semiconductor substrate and adjoins the gate structure in the first cross-section.Type: ApplicationFiled: May 27, 2022Publication date: November 30, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wang-Chun Huang, Hou-Yu Chen, Jin Cai, Chih-Hao Wang
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Publication number: 20230369466Abstract: Semiconductor structures and methods of forming the same are provided. A semiconductor structure according to the present disclosure includes at least one first semiconductor element and at least one second semiconductor element over a substrate, a dielectric fin disposed between the at least one first semiconductor element and the at least one second semiconductor element, a first work function metal layer wrapping around each of the at least one first semiconductor element and extending continuously from the at least one first semiconductor element to a top surface of the dielectric fin, and a second work function metal layer disposed over the at least one second semiconductor element and the first work function metal layer.Type: ApplicationFiled: July 24, 2023Publication date: November 16, 2023Inventors: Wang-Chun Huang, Hou-Yu Chen, Kuan-Lun Cheng, Chih-Hao Wang
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Publication number: 20230268344Abstract: A device includes a transistor, a backside via, and a pair of sidewall spacers. The transistor includes a gate structure, a channel layer surrounded by the gate structure, and a first source/drain structure and a second source/drain structure connected to the channel layer. The backside via is under and connected to the first source/drain structure and includes a first portion, a second portion between the first portion and the first source/drain structure, and a third portion tapering from the first portion to the second portion in a cross-sectional view. The pair of sidewall spacers are on opposite sidewalls of the second portion of the backside via but not on opposite sidewalls of the first portion of the backside via.Type: ApplicationFiled: April 21, 2023Publication date: August 24, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wang-Chun HUANG, Hou-Yu CHEN, Kuan-Lun CHENG, Chih-Hao WANG
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Patent number: 11735647Abstract: Semiconductor structures and methods of forming the same are provided. A semiconductor structure according to the present disclosure includes at least one first semiconductor element and at least one second semiconductor element over a substrate, a dielectric fin disposed between the at least one first semiconductor element and the at least one second semiconductor element, a first work function metal layer wrapping around each of the at least one first semiconductor element and extending continuously from the at least one first semiconductor element to a top surface of the dielectric fin, and a second work function metal layer disposed over the at least one second semiconductor element and the first work function metal layer.Type: GrantFiled: April 9, 2021Date of Patent: August 22, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wang-Chun Huang, Hou-Yu Chen, Kuan-Lun Cheng, Chih-Hao Wang
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Publication number: 20230253483Abstract: A semiconductor device structure is provided. The semiconductor device structure includes multiple first semiconductor nanostructures over a first semiconductor fin and multiple second semiconductor nanostructures over a second semiconductor fin. A topmost second semiconductor nanostructure of the second semiconductor nanostructures is thinner than one or more of lower semiconductor nanostructures of the second semiconductor nanostructures. The semiconductor device structure also includes a first metal gate stack wrapped around the first semiconductor nanostructures. The semiconductor device structure further includes a second metal gate stack wrapped around the second semiconductor nano structures.Type: ApplicationFiled: April 21, 2023Publication date: August 10, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wang-Chun Huang, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang
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Patent number: 11715781Abstract: A semiconductor device includes a substrate, two source/drain (S/D) regions over the substrate, a channel region between the two S/D regions and including a semiconductor material, a deposited capacitor material (DCM) layer over the channel region a dielectric layer over the DCM layer and a metallic gate electrode layer over the dielectric layer.Type: GrantFiled: February 26, 2020Date of Patent: August 1, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wang-Chun Huang, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang
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Publication number: 20230187545Abstract: An integrated circuit (IC) structure with a nanowire power switch device and a method of forming the IC structure are disclosed. The IC structure includes a front end of line (FEOL) device layer having a plurality of active devices, a first back end of line (BEOL) interconnect structure on the (FEOL) device layer, and a nanowire switch on the first BEOL interconnect structure. A first end of the nanowire switch is connected to an active device of the plurality of active devices through the first BEOL interconnect structure. The IC structure further includes a second BEOL interconnect structure on the nanowire switch. A second end of the nanowire switch is connected to a power source through the second BEOL interconnect structure and the second end is opposite to the first end.Type: ApplicationFiled: February 6, 2023Publication date: June 15, 2023Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Li-Yang CHUANG, Ching-Wei TSAI, Wang-Chun HUANG, Kuan-Lun CHENG
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Patent number: 11640989Abstract: A structure and formation method of a semiconductor device is provided. The method includes forming a semiconductor stack having first sacrificial layers and first semiconductor layers laid out alternately. The method also includes patterning the semiconductor stack to form a first structure and a second structure. The method further includes replacing the second structure with a third structure having second sacrificial layers and second semiconductor layers laid out alternately. In addition, the method includes removing the first sacrificial layers in the first structure and the second sacrificial layers in the third structure. The method includes forming a first metal gate stack and a second metal gate stack to wrap around each of the first semiconductor layers in the first structure and each of the second semiconductor layers in the third structure, respectively.Type: GrantFiled: February 7, 2022Date of Patent: May 2, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wang-Chun Huang, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang
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Patent number: 11637101Abstract: A semiconductor device includes a gate structure, a source/drain epitaxial structure, a front-side interconnection structure, a backside via, an isolation material, and a sidewall spacer. The source/drain epitaxial structure is on a side of the gate structure. The front-side interconnection structure is on a front-side of the source/drain epitaxial structure. The backside via is connected to a backside of the source/drain epitaxial structure. The isolation material is on a side of the backside via and in contact with the gate structure. The sidewall spacer is sandwiched between the backside via and the isolation material. A height of the isolation material is greater than a height of the sidewall spacer.Type: GrantFiled: December 8, 2020Date of Patent: April 25, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wang-Chun Huang, Hou-Yu Chen, Kuan-Lun Cheng, Chih-Hao Wang
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Patent number: 11610805Abstract: A method includes, through a backside of a substrate, removing a portion of a gate structure to form a trench that isolates the gate structure in two portions. The method further includes depositing a sacrificial material within the trench and conformally along sidewalls of the trench, filling a remainder of the trench with a first dielectric material, partially removing the sacrificial material to leave an opening between the first dielectric material and the gate structure, and filling the opening with a work-function metal.Type: GrantFiled: February 26, 2021Date of Patent: March 21, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wang-Chun Huang, Yu-Xuan Huang, Hou-Yu Chen, Kuan-Lun Cheng, Chih-Hao Wang
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Publication number: 20230064635Abstract: In an exemplary aspect, the present disclosure is directed to a device. The device includes a semiconductor substrate, a stack of semiconductor layers over the semiconductor substrate, a gate structure over and between the stack of semiconductor layers, where the gate structure engages with the stack of semiconductor layers. Moreover, the device also includes a silicide layer extending along sidewall surfaces of the stack of semiconductor layers, and a source/drain feature on a sidewall surface of the silicide layer.Type: ApplicationFiled: August 30, 2021Publication date: March 2, 2023Inventors: Yu-Xuan Huang, Wang-Chun Huang, Yi-Bo Liao, Cheng-Ting Chung, Hou-Yu Chen, Kuan-Lun Cheng, Wei Ju Lee
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Patent number: 11575034Abstract: An integrated circuit (IC) structure with a nanowire power switch device and a method of forming the IC structure are disclosed. The IC structure includes a front end of line (FEOL) device layer having a plurality of active devices, a first back end of line (BEOL) interconnect structure on the (FEOL) device layer, and a nanowire switch on the first BEOL interconnect structure. A first end of the nanowire switch is connected to an active device of the plurality of active devices through the first BEOL interconnect structure. The IC structure further includes a second BEOL interconnect structure on the nanowire switch. A second end of the nanowire switch is connected to a power source through the second BEOL interconnect structure and the second end is opposite to the first end.Type: GrantFiled: March 17, 2021Date of Patent: February 7, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Li-Yang Chuang, Ching-Wei Tsai, Wang-Chun Huang, Kuan-Lun Cheng
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Publication number: 20220384250Abstract: A semiconductor structure includes a gate structure surrounding a plurality of channels and a cut feature that electrically isolates two separate portions of the gate structure. The cut feature comprises an outer layer having a work-function metal, and an inner layer comprising a dielectric material. The cut feature extends above a top surface of the gate structure.Type: ApplicationFiled: August 9, 2022Publication date: December 1, 2022Inventors: Wang-Chun Huang, Yu-Xuan Huang, Hou-Yu Chen, Kuan-Lun Cheng, Chih-Hao Wang
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Publication number: 20220384620Abstract: Semiconductor structures and methods of forming the same are provided. A semiconductor structure according to the present disclosure includes at least one first semiconductor element and at least one second semiconductor element over a substrate, a dielectric fin disposed between the at least one first semiconductor element and the at least one second semiconductor element, a first work function metal layer wrapping around each of the at least one first semiconductor element and extending continuously from the at least one first semiconductor element to a top surface of the dielectric fin, and a second work function metal layer disposed over the at least one second semiconductor element and the first work function metal layer.Type: ApplicationFiled: August 10, 2022Publication date: December 1, 2022Inventors: Wang-Chun Huang, Hou-Yu Chen, Kuan-Lun Cheng, Chih-Hao Wang