Patents by Inventor WANG-JHE HUANG

WANG-JHE HUANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11580928
    Abstract: The present disclosure relates to a circuit of controlling a common voltage of a liquid crystal panel. According to an embodiment of the present disclosure, a voltage control circuit is configured to provide a common voltage to a common electrode of a liquid crystal panel. The liquid crystal panel includes M rows and N columns of pixel units. Each pixel unit is coupled to the common electrode. The voltage control circuit includes an operational amplifier arranged in a negative feedback configuration. The operational amplifier includes: an input stage, a gain stage and an output stage. The output stage includes a second NMOS transistor and a second PMOS transistor. A gate of the second NMOS transistor receives a first control signal, a drain of the second NMOS transistor is coupled to a gate of a first PMOS transistor, and a source of the second NMOS transistor is coupled to a second reference voltage.
    Type: Grant
    Filed: June 23, 2022
    Date of Patent: February 14, 2023
    Assignee: OMNIVISION TDDI ONTARIO LIMITED PARTNERSHIP
    Inventor: Wang-Jhe Huang
  • Publication number: 20220415281
    Abstract: A voltage control circuit provides a common voltage to a common electrode of a liquid crystal panel. The liquid crystal panel includes pixel units, each of which is coupled to the common electrode. The circuit includes an operational amplifier in a negative feedback configuration. The operational amplifier includes: an input stage, a gain stage and an output stage including a second NMOS transistor and a second PMOS transistor. A gate of the second NMOS transistor receives a first control signal, and a drain and a source of the second NMOS transistor are respectively coupled to a gate of a first PMOS transistor and a second reference voltage. A gate of the second PMOS transistor receives a second control signal, and a drain and a source of the second PMOS transistor is respectively coupled to a gate of a first NMOS transistor and a third reference voltage.
    Type: Application
    Filed: June 23, 2022
    Publication date: December 29, 2022
    Inventor: WANG-JHE HUANG