Abstract: A semiconductor device is provided. The semiconductor device comprising a first fin pattern and a second fin pattern which are separated by a first isolation trench and extend in a first direction, a third fin pattern which is spaced apart from the first fin pattern in a second direction intersecting the first direction and extends in the first direction, a fourth fin pattern which is separated from the third fin pattern by a second isolation trench, a first gate structure which intersects the first fin pattern and has a portion extending along an upper surface of the first fin pattern, a second gate structure which intersects the second fin pattern and has a portion extending along an upper surface of the second fin pattern and a first element isolation structure which fills the second isolation trench and faces a short side of the first gate structure.

Abstract: An OS-independent peripheral plug-and-play and driver update method for embedded system and firmware data transmission method for embedded system platform is provided. The method includes: determining whether a peripheral device is connected to the embedded system host; when the peripheral device is connected to the embedded system host, acquire the ID of the peripheral device; connecting to a firmware server; according to the ID, acquiring a driver; packing the driver into a firmware and transmitting to the embedded system host; and performing a firmware update.

Abstract: A semiconductor device is provided. The semiconductor device comprising a first fin pattern and a second fin pattern which are separated by a first isolation trench and extend in a first direction, a third fin pattern which is spaced apart from the first fin pattern in a second direction intersecting the first direction and extends in the first direction, a fourth fin pattern which is separated from the third fin pattern by a second isolation trench, a first gate structure which intersects the first fin pattern and has a portion extending along an upper surface of the first fin pattern, a second gate structure which intersects the second fin pattern and has a portion extending along an upper surface of the second fin pattern and a first element isolation structure which fills the second isolation trench and faces a short side of the first gate structure.

Abstract: A backlight module is provided. The backlight module includes a backlight control circuit and a plurality of multiple light-emitting elements coupled in series and coupled to the backlight control circuit. The backlight control circuit transmits a packet. Each of the light-emitting elements compares an address of the packet with an individual address of each of the light-emitting elements. When the address of the packet matches the individual address of a target light-emitting element of the light-emitting elements, the target light-emitting element emits light according to a light-emitting data of the packet. Each of the light-emitting elements transmits the packet to a next light-emitting element.

Abstract: The present disclosure discloses an antibacterial film structure. The antibacterial film structure comprises a silica base layer, an organic hydrophilic antibacterial layer, and a silica protective layer. The organic hydrophilic antibacterial layer is disposed on the silica base layer, and the silica protective layer is disposed on the organic hydrophilic antibacterial layer.

Abstract: An anti-fog lens including a lens and an anti-fog layer. The lens having a first surface and a second surface. The anti-fog layer is disposed on a side of the first surface and a side of the second surface, and includes a modified cellulose triacetate (TAC).

Abstract: The disclosure provides a modified UDP-GlcNAc:Lysosomal Enzyme GlcNAc-1-phosphotransferase with enhanced ability to phosphorylate lysosomal enzymes and methods of use thereof.

Abstract: A semiconductor device includes a first active structure on a substrate including a first epitaxial pattern, a second epitaxial pattern and a first channel pattern between the first epitaxial pattern and the second epitaxial pattern, the first channel pattern including at least one channel pattern stacked on the substrate. A first gate structure is disposed on top and bottom surfaces of the first channel pattern. A second active structure on the substrate and includes the second epitaxial pattern, a third epitaxial pattern and a second channel pattern between the second epitaxial pattern and the third epitaxial pattern in the first direction. The second channel pattern includes at least one channel pattern stacked on the substrate. The number of stacked second channel patterns is greater than the number of stacked first channel patterns. A second gate structure is disposed on top and bottom surfaces of the second channel pattern.

Abstract: A semiconductor device is provided including a substrate, a first gate structure, a first contact plug and a power rail. The substrate includes first and second cell regions extending in a first direction, and a power rail region connected to each of opposite ends of the first and second cell regions in a second direction. The first gate structure extends in the second direction from a boundary area between the first and second cell regions to the power rail region. The first contact plug is formed on the power rail region, and contacts an upper surface of the first gate structure. The power rail extends in the first direction on the power rail region, and is electrically connected to the first contact plug. The power rail supplies a turn-off signal to the first gate structure through the first contact plug to electrically insulate the first and second cell regions.

Abstract: A semiconductor device includes a substrate having cell areas and power areas that are alternately arranged in a second direction. Gate structures extend in the second direction. The gate structures are spaced apart from each other in a first direction perpendicular to the second direction. Junction layers are arranged at both sides of each gate structure. The junction layers are arranged in the second direction such that each of the junction layer has a flat portion that is proximate to the power area. Cutting patterns are arranged in the power areas. The cutting patterns extend in the first direction such that each of the gate structures and each of the junction layers in neighboring cell areas are separated from each other by the cutting pattern.

Abstract: The disclosure provides a modified UDP-GlcNAc:Lysosomal Enzyme GlcNAc-1-phosphotransferase with enhanced ability to phosphorylate lysosomal enzymes and methods of use thereof.

Abstract: A semiconductor device includes a first active structure on a substrate including a first epitaxial pattern, a second epitaxial pattern and a first channel pattern between the first epitaxial pattern and the second epitaxial pattern, the first channel pattern including at least one channel pattern stacked on the substrate. A first gate structure is disposed on top and bottom surfaces of the first channel pattern. A second active structure on the substrate and includes the second epitaxial pattern, a third epitaxial pattern and a second channel pattern between the second epitaxial pattern and the third epitaxial pattern in the first direction. The second channel pattern includes at least one channel pattern stacked on the substrate. The number of stacked second channel patterns is greater than the number of stacked first channel patterns. A second gate structure is disposed on top and bottom surfaces of the second channel pattern.

Abstract: A semiconductor device includes an active region extending in a first direction on a substrate, a buried conductive layer disposed adjacent to the active region on the substrate and extending in the first direction, a gate electrode intersecting the active region and extending in a second direction crossing the first direction, a source/drain layer disposed on the active region on one side of the gate electrode, a gate isolation pattern disposed on the buried conductive layer so as to be disposed adjacent to one end of the gate electrode, and extending in the first direction, and a contact plug disposed on the source/drain layer, electrically connected to the buried conductive layer, and in contact with the gate isolation pattern.

Abstract: An integrated circuit device may include a fin-type active region extending in a first direction on a substrate; an insulating separation structure extending in a second direction that intersects the first direction on the fin-type active region; a pair of split gate lines spaced apart from each other with the insulating separation structure therebetween and extending in the second direction to be aligned with the insulating separation structure; a pair of source/drain regions located on the fin-type active region and spaced apart from each other with the insulating separation structure therebetween; and a jumper contact located over the insulating separation structure and connected between the pair of source/drain regions.

Abstract: An integrated circuit device may include a fin-type active region extending in a first direction on a substrate; an insulating separation structure extending in a second direction that intersects the first direction on the fin-type active region; a pair of split gate lines spaced apart from each other with the insulating separation structure therebetween and extending in the second direction to be aligned with the insulating separation structure; a pair of source/drain regions located on the fin-type active region and spaced apart from each other with the insulating separation structure therebetween; and a jumper contact located over the insulating separation structure and connected between the pair of source/drain regions.

Abstract: An egg cooking system includes two woks and each of the woks receives oil from an oil supply member. A support member is driven by a driving unit to allow one egg to be put in the at least one standby portion and the egg is pressed by the pressing member. A cracking member cracks the egg and the pressing unit moves toward the direction that the egg is located so that a claw is opened, and the egg flows into one of the woks. The egg is cooked for a pre-set time, and is dropped into the other wok to be cooked. The cooked egg is then dropped to a plate. The pressing unit presses the egg shell of the egg to further open the claw, and the egg shell drops into a garbage can.

Abstract: A semiconductor device includes an active region extending in a first direction on a substrate, a buried conductive layer disposed adjacent to the active region on the substrate and extending in the first direction, a gate electrode intersecting the active region and extending in a second direction crossing the first direction, a source/drain layer disposed on the active region on one side of the gate electrode, a gate isolation pattern disposed on the buried conductive layer so as to be disposed adjacent to one end of the gate electrode, and extending in the first direction, and a contact plug disposed on the source/drain layer, electrically connected to the buried conductive layer, and in contact with the gate isolation pattern.

Abstract: An embodiment includes a snap-fit temple interface of a lens. The snap-fit temple interface includes a first snap-fit feature and a second snap-fit feature. The first snap-fit feature of the lens is configured to be engaged with a first corresponding snap-fit feature of a temple assembly. The first snap-fit feature is configured to be engaged with the first corresponding snap-fit feature by a first movement of the lens in a first direction relative to the temple assembly followed by a second movement of the lens in a second direction relative to the temple assembly. The second snap-fit feature of the lens is configured to be engaged with a second corresponding snap-fit feature of the temple assembly. The second snap-fit feature is configured to be engaged with the second snap-fit feature by the second movement of the lens in the second direction relative to the temple assembly. The first direction is substantially perpendicular to the second direction.

Abstract: A semiconductor device includes a substrate having cell areas and power areas that are alternately arranged in a second direction. Gate structures extend in the second direction. The gate structures are spaced apart from each other in a first direction perpendicular to the second direction. Junction layers are arranged at both sides of each gate structure. The junction layers are arranged in the second direction such that each of the junction layer has a flat portion that is proximate to the power area. Cutting patterns are arranged in the power areas. The cutting patterns extend in the first direction such that each of the gate structures and each of the junction layers in neighboring cell areas are separated from each other by the cutting pattern.