Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for training a neural network to perform a machine learning task through reinforcement learning. In one aspect, the training uses importance weights generated using standardized absolute deviations of quality scores generated by the neural network for candidate network outputs.

Abstract: Aspects are provided which allow a UE to apply CFO compensation to resolve mismatched RAPIDs caused by uplink Doppler shifts in HST deployments. The UE obtains one or more RARs each including a RAPID, where each of the RARs is responsive to a random access message including a preamble. The UE determines, in each of a threshold number of the one or more RARs, that the RAPID of a corresponding RAR is different than the preamble of a corresponding random access message. The UE then offsets a carrier frequency for each of one or more subsequent random access messages in response to the determination. As a result, mismatched RAPIDs due to uplink Doppler shifts may be avoided and RACH success rates may thereby be improved.

Abstract: An integrated circuit is provided having a base with a first dielectric layer formed thereon. A second dielectric layer is formed over the first dielectric layer. A third dielectric layer is formed in spaced-apart strips over the second dielectric layer. A first trench opening is formed through the first and second dielectric layers between the spaced-apart strips of the third dielectric layer. A second trench opening is formed contiguously with the first trench opening through the first dielectric layer between the spaced-apart strips of the third dielectric layer. Conductor metals in the trench openings form self-aligned trench interconnects.

Abstract: A video game includes: (i) a graphic user interface that presents a user a simulation of real-life events; (ii) a content database containing a collection of actual photos and videos of real-life events; (iii) a simulation engine that, presents a plurality of possible actions to the user, receives a selection of at least one of the actions from the user, identifies at least one photo or video in the database that is associated with the user-selected action, and presents the user with a result in response to the selection, wherein the result includes the identified photo or video; (iv) a content update module that receives updated photo or video content from one or more content distributors, creates an association element for the updated content and an available action in the game, and includes the updated content and association element in the content database; and (v) a scoring module.

Abstract: A shoulder rest (50) comprises an attachment piece (60), an abutment piece (62), and a padding piece (64) and is adapted for supporting a stringed instrument (80) such as violin or viola during playing, wherein the attachment piece (60) is adapted to clip onto an end button (82) of the stringed instrument (80) such that the contact surface between the stringed instrument (80) and the shoulder rest (50) is juxtaposing a bottom block of the stringed instrument (80).

Abstract: A shoulder rest (50) comprises an attachment piece (60), an abutment piece (62), and a padding piece (64) and is adapted for supporting a stringed instrument (80) such as violin or viola during playing, wherein the attachment piece (60) is adapted to clip onto an end button (82) of the stringed instrument (80) such that the contact surface between the stringed instrument (80) and the shoulder rest (50) is juxtaposing a bottom block of the stringed instrument (80).

Abstract: A method of manufacturing a 3-D spiral stacked inductor is provided having a substrate with a plurality of turns in a plurality of levels wherein the number of levels increases from an inner turn to the outer turn of the inductor. First and second connecting portions are respectively connected to an inner turn and an outermost turn, and a dielectric material contains the first and second connecting portions and the plurality of turns over the substrate.

Abstract: An improved technique of utilizing a centralized control protocol for lighting devices such as DALI. A technique is disclosed for utilizing such protocols in a wireless environment. The first step involves associating particular slave devices with a specified master control device, and a second step involves associating specific functions within the master device with specific slave devices.

Abstract: A video game includes: (i) a graphic user interface that presents a user a simulation of real-life events; (ii) a content database containing a collection of actual photos and videos of real-life events; (iii) a simulation engine that, presents a plurality of possible actions to the user, receives a selection of at least one of the actions from the user, identifies at least one photo or video in the database that is associated with the user-selected action, and presents the user with a result in response to the selection, wherein the result includes the identified photo or video; (iv) a content update module that receives updated photo or video content from one or more content distributors, creates an association element for the updated content and an available action in the game, and includes the updated content and association element in the content database; and (v) a scoring module.

Abstract: An integrated circuit and manufacturing method therefor is provided having a base with a first dielectric layer formed thereon. A second dielectric layer is formed over the first dielectric layer. A third dielectric layer is formed in spaced-apart strips over the second dielectric layer. A first trench opening is formed through the first and second dielectric layers between the spaced-apart strips of the third dielectric layer. A second trench opening is formed contiguously with the first trench opening through the first dielectric layer between the spaced-apart strips of the third dielectric layer. Conductor metals in the trench openings form self-aligned trench interconnects.

Abstract: A new method of forming shallow trench isolations has been described. A silicon semiconductor substrate is provided. A silicon nitride layer is deposited overlying the substrate. A polysilicon layer is deposited overlying the silicon nitride layer. An oxidation mask is deposited overlying the polysilicon layer. The oxidation mask, polysilicon layer, silicon nitride layer, and the silicon semiconductor substrate are patterned to form trenches for planned shallow trench isolations. The silicon semiconductor substrate exposed within the trenches is oxidized to form an oxide liner layer within the trenches wherein the oxidation mask prevents oxidation of the polysilicon layer. Thereafter the oxidation mask is removed. A trench oxide layer is deposited overlying the liner oxide layer and filling the trenches.

Abstract: A MOSFET device structure formed on a silicon on insulator layer, and a process sequence employed to fabricate said MOSFET device structure, has been developed. The process features insulator filled, shallow trench isolation (STI) regions formed in specific locations of the MOSFET device structure for purposes of reducing the risk of parasitic transistor formation underlying a gate structure junction. After formation of either a “T” shaped, or an “H” shaped gate structure, body contact regions of a first conductivity type are formed adjacent to both an STI region and to a component of the gate structure. Formation of a source/drain region of a second conductivity type located on the opposite side of the same STI region, and the same gate structure component, is next performed. Unwanted parasitic transistor formation, which can occur underlying the gate structure via the body contact region and the source/drain region, is prevented by the presence of the separating STI region.

Abstract: A MOSFET device structure formed on a silicon on insulator layer, and a process sequence employed to fabricate said MOSFET device structure, has been developed. The process features insulator filled, shallow trench isolation (STI) regions formed in specific locations of the MOSFET device structure for purposes of reducing the risk of parasitic transistor formation underlying a gate structure junction. After formation of either a “T” shaped, or an “H” shaped gate structure, body contact regions of a first conductivity type are formed adjacent to both an STI region and to a component of the gate structure. Formation of a source/drain region of a second conductivity type located on the opposite side of the same STI region, and the same gate structure component, is next performed. Unwanted parasitic transistor formation, which can occur underlying the gate structure via the body contact region and the source/drain region, is prevented by the presence of the separating STI region.

Abstract: A silicon-on-insulator semiconductor device is provided in which a single wafer die contains a transistor over an insulator layer to form a fully depleted silicon-on-insulator device and a transistor formed in a semiconductor island over an insulator structure on the semiconductor wafer forms a partially depleted silicon-on-insulator device.

Abstract: A 3-D spiral stacked inductor is provided having a substrate with a plurality of turns in a plurality of levels wherein the number of levels increases from an inner turn to the outer turn of the inductor. First and second connecting portions are respectively connected to an inner turn and an outermost turn, and dielectric material contains the first and second connecting portions and the plurality of turns over the substrate.

Abstract: A parallel spiral stacked inductor and manufacturing method therefore is provided. A substrate has a plurality of turns in a plurality of levels, the plurality of turns having a center proximate and a center distal ends. A first plurality of vias connecting the center proximate ends of the plurality of turns and a second plurality of vias connecting the center distal ends of the plurality of turns. A first connecting portion connects to the center proximate ends of the plurality of turns and a second connecting portion connecting to the center distal end of the plurality of turns. A dielectric material contains the inductor.

Abstract: An integrated circuit and manufacturing method therefor is provided having a base with a first dielectric layer formed thereon. A second dielectric layer is formed over the first dielectric layer. A third dielectric layer is formed in spaced-apart strips over the second dielectric layer. A first trench opening is formed through the first and second dielectric layers between the spaced-apart strips of the third dielectric layer. A second trench opening is formed contiguously with the first trench opening through the first dielectric layer between the spaced-apart strips of the third dielectric layer. Conductor metals in the trench openings form self-aligned trench interconnects.

Abstract: A method and apparatus for shallow trench isolation. First, a layer of silicon nitride (SiN) is deposited over a semiconductor substrate. A layer of polysilicon is then deposited over the silicon nitride layer. A layer of tetraethylorthosilicate (TEOS) is deposited over the polysilicon layer. Mask and etch steps are performed to form an opening that extends through the TEOS layer and through the polysilicon layer. An etch step is then performed to etch the exposed side surfaces of the polysilicon layer. Thereby, the exposed side surfaces of the polysilicon layer are moved laterally. An etch step is then performed so as to form a trench that extends into the semiconductor substrate. Dielectric material is deposited such that the dielectric material fills the trench and fills the opening that extends through the polysilicon layer and the silicon nitride layer. The substrate is then polished using a chemical mechanical polishing process.

Abstract: A method of manufacturing a shallow trench isolation using a polishing step with reduced dishing. A pad layer, a polish stop layer, a buffer layer and a hard mask layer are formed over a substrate. The hard mask layer has a hard mask opening. We etch a trench opening in the buffer layer, the polish stop layer, the pad layer and form a trench in the substrate using the hard mask layer as an etch mask. We form an oxide trench liner layer along the sidewalls of the trench and an oxide buffer liner layer on the sidewalls of the buffer layer using a thermal oxidation. The hard mask layer prevents the oxidation of the top surface of the buffer layer during the oxidation of the oxide trench liner. This prevents the buffer layer from being consumed by the oxidation and leaves the buffer layer to act in the subsequent chemical-mechanical polish (CMP) step. Next, an insulating layer is formed at least partially filling the trench.

Abstract: A method to form SOI devices using wafer bonding. A first substrate is provided having trenches in a first side. A first insulating layer is formed over the first side of the first substrate and filling the trenches. We planarize the first insulating layer to form isolation regions (e.g., STI). The three embodiments of the invention planarize the first insulating layer to different levels. In the second embodiment, the first insulating layer is etched back to form a recess. This recess later forms an air gap. We provide a second substrate having a second insulating layer over a first side of the second substrate. We bond the second insulating layer to the first insulating layer. Next, we thin the first substrate from the second side to expose the first insulating layer to form active areas between the isolation regions. Lastly, devices are formed in and on the active areas.