Abstract: An information handling system includes a number of processors, each connected to a processor bus, a memory controller connected to the processor bus which controls access to a system memory, a system controller, and one or more I/O controllers connected to the system bus where the system controller controls access to the system bus by all of the elements connected to the system bus, and the memory controller provides an efficient mechanism for handling data access to memory on read commands if a coherency response is modified. Combiner-prioritization logic in the memory controller includes logic in response to two additional inputs not shown in the prior art. The first logic responds to a read command and signals when a response window currently being combined is from a read command, and the second logic signals that the memory has an intervention buffer available to allow intervention.

Abstract: Circuitry within a system memory controller of a data processing system enables an M-bit processor to address a memory location that requires an N-bit address, wherein N is greater than M. Thus, a less than 48-bit processor will be able to access IPL code resident within a 48-bit memory system. An M-bit address is received from a processor and then extended into an N-bit address with a mask of N-M bits. The extended address is compared with an N-bit address representing the memory location to be addressed, and the extended address is then selected to access the memory location when the extended address equals the N-bit address representing the memory location.

Abstract: PowerPC external control instructions are utilized to pass a translated address to a transfer engine located in the system memory controller, together with previously transferred parameters into control registers within the memory controller. An accelerated data movement is accomplished between system memory and an input/output device with a minimum of processor overhead and bus bandwidth utilization. This method is useful for transferring large amounts of data between memory and such devices as graphics adapters or multimedia devices.

Abstract: An information handling system includes one or more processing units, a data management unit, connected to the processor data bus, to a memory system, and to a I/O bus, an address management unit, connected to the processor address bus, to the memory system, to an I/O bus, and to a system initialization storage device, storing an initialization routine and data, wherein system initialization includes, in response to an Initial Program Load Read command issued by a processor, the steps of returning initialization data to the processor if the IPL read is accepted (IPL data available) by a device attached to the processor bus; if no device attached to the processor bus responds with IPL data, passing the read IPL command to the I/O bus under control of the data management unit; if the read command is accepted by an I/O controller attached to the I/O bus, returning initialization data to the processor; if no I/O controller accepts the IPL read command, passing the read command to the system initialization storage

Abstract: An information handling system includes a system memory controller having a control register in which a bit is reserved for Doze mode control. The Doze control bit is set by system software whenever it places any processor into Doze mode. Until this bit is set, there is no wake up signal issued nor any performance lost. Whenever this control bit is set, the memory controller sends a signal to the system arbiter that informs it to issue a "wake up signal" before issuing an address bus grant, in time to satisfy the processor wake up latency. In addition, if the system arbiter receives another address bus request within a predefined time window, the "wake up signal" is held active without adding to the bus grant latency. If maximum system performance is desired (all processors out of Doze mode), the system software resets the Doze mode control bit in the memory controller, which removes the signal to the system arbiter which controls the wake up signal and removes the added latency for granting the bus.

Abstract: An information handling system includes one or more processing units, a data bus management unit, connected to the processor data bus, to a memory system, and to an I/O bus, an address management unit, connected to the processor address bus, to the memory system, to the I/O bus, and one or more I/O controllers, where the address and data management units isolate the processor buses from the I/O bus and the memory system.