Abstract: The invention comprises an array of ADCs, associated either with spatially separated signal input devices such as for example antennae, or with a single signal input device and a plurality of filters having a variable phase delay, which provide a digital output which is processed to remove spurious signals introduced by the ADCs thereby providing a linearised output. An array of N antennae with respective band pass filters and ADCs (10) feeds received signals into a frequency channelisation device (12) which divides each of the N input streams into M lower bandwidth streams for distribution. In a first path, an FFT (14) is used to detect signal of interest, to determine where intermodulation products arm likely to exist and to provide course data for the spatial processing used in the signal separation sub-systems. The second path (16) includes the detection and separation of co-channels signals. Signal classification techniques are then used to identify spurious sir, which are then removed.

Abstract: The generation of number theory mappings and their application to the addressing of matrix structures through the provision of an address generator which is optimized for the general task of applying "on-the-fly" number theory mappings to matrix operands as they are fetched from memory.

Abstract: A cellular floating-point serial pipelined multiplier arranged to accept two synchronous digit serial data streams in floating-point format and to output one identically formatted stream is the floating-point product of the synchronous input members. The multiplier includes a delay circuit (1) for the X operand and a digit re-ordering/delay circuit (2) for the Y operand connected to a pipelined addition circuit (3) which outputs the product through a delay cell (6). A MODE control signal propagation and generation circuit (4) is also connected to the pipelined addition circuit (3) and to the digit re-ordering/delay circuit (2), and a cell differentiation circuit (5) is connected to control the pipelined addition circuit (3) and the digit re-ordering/delay circuit (2) and the X operand delay circuit (1).

Abstract: A three-dimensional systolic architecture for beamforming according to convolve signals from an array with sets of weighting coefficients using a one dimensional array of similar modules with finite impulse response filter elements with outputs directed into pipelining register stacks and propagated to the stack boundaries for summing in accumulator arrays and demultiplexing.

Abstract: The method of self repair of large scale integrated circuit modules (LSI or VLSI) in which a series of systolic processing elements (SPE's) arranged in rows (V and H) normal to each other, have sequential paths between elements biased so that normally the data being processed follows the vertical and horizontal rows to maintain a selected topography including the steps of establishing the functionality of each SPE, bypassing any unfunctional SPE by directing the data path of any row to a rear SPE in the nest row, and directing the data path from the said near SPE back to the original row to maintain the original topography.