Abstract: A wide area lamp for use in hazardous locations includes a metal halide lamp excited by a ballast. The lamp is mounted within an explosion-proof transparent globe and metal lamp guard secured to a metal vault. The vault is divided into two compartments. One compartment houses a ballast for the lamp. That compartment is filled with a potting compound to eliminate any arcing in the high voltage excitation circuit. The other compartment is enclosed, but accessible for making necessary electrical connectors to a power feed cord.

Abstract: A fluorescent tube lighting fixture includes a tubular main frame member which also acts as a conduit for routing wires between the ballast and the lamp holders. A frame extension the form of a Tee is threaded onto one end of the main frame member; and another portion of the Tee receives an adapter which secures the end cap to the fixture. Wire is routed through the adapter, and through the Tee into the main tubular frame member, all of which portions cooperate to act as a protective conduit for the power cord, with a single opening in the end cap. By removing a single compression nut, the end cap and lamp guard can be moved to gain access to the interior of the lamp for maintenance.

Abstract: A fluorescent lamp for use in special applications includes an electrodeless envelope of glass or other light transmissive material carrying fluorescent material within the envelope. An RF energy source and coupler are embedded in epoxy as an integral power unit, thereby isolating the power unit from the hazardous environment. The power unit and the envelope are shaped in complementary form such that the coupler and envelope are in energy-transfer relation to excite the lamp, but the envelope may be removed from the power unit to re-lamp the fixture.

Abstract: A portable electric lamp suitable for use in hazardous locations includes a fixture which is purged continuously with air during operation. Pressurized air is introduced at an input end of the fixture, through a plenum which establishes a generally laminar flow of air through the fixture during purging. To insure that the fixture is satisfactorily purged before power is applied to the lamps, differential pressure is measured over a precision orifice at the discharge end of the lamp, and total flow is determined. During the start-up cycle, pressure within the fixture must exceed a predetermined minimum threshold; but following start-up, the operating pressure may drop lower than the initial minimum pressure, as long as a positive pressure is maintained within the fixture.

Abstract: An improved diaphragm sensor employs silicon-on-silicon technology and has monolithic integrated signal conditioning circuitry. The support circuitry minimizes the effects of stray capacitance and may be configured to provide either analog or digital output to external terminals. It has a wide band of linearity and is particularly useful for accurately measuring pressures less than 0.5 PSI. The sensor is constructed by joining a silicon top plate having a mechanical pressure stop, a reduced thickness silicon diaphragm and a back plate having CMOS circuitry thereon. These components are bonded together by eutectic soldering.

Abstract: A data processing system having a bus system for data communication employs a bus splitting circuit. This bus splitting circuit permits selective connection and isolation of individual buses of the bus system. A more flexible assortment of data communications paths among logic blocks coupled to the bus system is permitted by this arrangement in which some logic blocks may be coupled during one state of the bus splitting circuit and decoupled during the other state of the bus splitting circuit. By separating some of the buses via the bus splitting circuit, dual data transfers using the split buses is possible. In a preferred embodiment at least one of the logic blocks is a memory which is coupled to more than one of the buses, thus permitting simultaneous read and write operations, dual read operations or dual write operations.

Abstract: An address decode scheme decodes address lines using a minimum number of electrical conductors and minimum area on the chip. Instead of decoding the true and the complementary signals of each address input using a PLA or static gate, the present decode scheme uses two sets of programmable transistors for respectively detecting zeros and ones on the address lines and for generating selected high and low decode signals in conjunction with precharge, discharge, and control transistors. This invention is equally effective in CMOS, NMOS, or PMOS technologies.