Patents by Inventor Watanabe Ryoichi

Watanabe Ryoichi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140175047
    Abstract: A method of manufacturing a printed circuit board, according to one embodiment, includes forming a circuit pattern and a via pad, which is disposed by being spaced apart from the circuit pattern and has concavo-convex patterns, on a first insulating layer; forming a second insulating layer on the circuit pattern and the via pad having the concavo-convex patterns formed thereon; forming a via hole by etching a portion of the second insulating layer on the via pad; and forming a copper foil layer on the second insulating layer having the via hole formed therein.
    Type: Application
    Filed: February 27, 2014
    Publication date: June 26, 2014
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Watanabe RYOICHI, Se Won Park
  • Patent number: 8680404
    Abstract: The present invention provides a printed circuit board including: a circuit pattern formed on a first insulating layer; a via pad disposed on the first insulating layer by being spaced apart from the circuit pattern, formed on a lower surface, where a via hole is formed, to have a cross section larger than that of the via hole, and having concavo-convex patterns; a second insulating layer formed on the via pad where the via hole is not formed and on the circuit pattern; and a copper foil layer formed on the second insulating layer and the via hole, and a method of manufacturing the same.
    Type: Grant
    Filed: February 5, 2010
    Date of Patent: March 25, 2014
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Watanabe Ryoichi, Se Won Park
  • Publication number: 20110100686
    Abstract: The present invention provides a printed circuit board including: a circuit pattern formed on a first insulating layer; a via pad disposed on the first insulating layer by being spaced apart from the circuit pattern, formed on a lower surface, where a via hole is formed, to have a cross section larger than that of the via hole, and having concavo-convex patterns; a second insulating layer formed on the via pad where the via hole is not formed and on the circuit pattern; and a copper foil layer formed on the second insulating layer and the via hole, and a method of manufacturing the same.
    Type: Application
    Filed: February 5, 2010
    Publication date: May 5, 2011
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Watanabe Ryoichi, Se Won Park