Abstract: In order to provide a fiber structure having excellent heat retention and wearing comfort and a garment obtained by using the same, there is provided a fiber structure containing: a viscose rayon fiber in an amount of more than 15% by mass and less than 40% by mass; a cation dyeable polyester filament yarn in an amount of more than 10% by mass and less than 45% by mass; a polyacrylic synthetic fiber in an amount of more than 25% by mass and less than 60% by mass; and a spandex fiber in an amount of more than 3% by mass and less than 15% by mass, wherein the fiber structure has a nap formed on a front surface or a back surface thereof.

Abstract: An image pickup device includes a first image sensor for photoelectrically converting subject light and generating an image, a second image sensor for photoelectrically converting the subject light and generating an image for a live view, a first optical member for transmitting the subject light and allowing the subject light to enter the first image sensor, and at the same time, reflecting the subject light, and a second optical member for leading the subject light reflected by the first optical member to the second image sensor and allowing the subject light to enter the second image sensor.

Abstract: An apparatus comprises a module which stores document information to which content that includes link character strings linked to other items on an item basis is caused to correspond, a first display control module which displays content on an arbitrary item stored as first content according to a user operation, a second display control module which lists the link character strings included in the displayed first content and displays them together with the first content, a selection module which selects, according to a user operation, a link character string displayed, and a third display control module which displays content on an item stored in such a manner that the item is linked to the selected link character string.

Abstract: A circuit on an end column of a divided memory array is formed by a block selection transistor having the same shape as that of a memory cell transistor. As the pattern of the connecting section between the main bit line and the sub-bit line is made in the same shape as that of the memory cell, it is possible to realize a pattern uniformity and to eliminate the need for using memory array dummy patterns.

Abstract: An image pickup device includes a first image sensor for photoelectrically converting subject light and generating an image, a second image sensor for photoelectrically converting the subject light and generating an image for a live view, a first optical member for transmitting the subject light and allowing the subject light to enter the first image sensor, and at the same time, reflecting the subject light, and a second optical member for leading the subject light reflected by the first optical member to the second image sensor and allowing the subject light to enter the second image sensor.

Abstract: A information display apparatus includes a content storage module, a controller, a specification module, and a marker information storage module. The controller controls a text to be displayed. The specification module specifies, based on a user's operation, a character string, as a marker display character string in the displayed text. The marker information storage module stores position information of the marker display character string within a storage region of the content storage module, and stores a stored time where the position information is stored as being related to the position information. The controller allows the text in an identifiable manner based on the position information, wherein a mode of the identifiable display is differed in accordance with time elapsed since the stored time for the marker display character string.

Abstract: A circuit on an end column of a divided memory array is formed by a block selection transistor having the same shape as that of a memory cell transistor. As the pattern of the connecting section between the main bit line and the sub-bit line is made in the same shape as that of the memory cell, it is possible to realize a pattern uniformity and to eliminate the need for using memory array dummy patterns.

Abstract: An apparatus comprises a module which stores document information to which content that includes link character strings linked to other items on an item basis is caused to correspond, a first display control module which displays content on an arbitrary item stored as first content according to a user operation, a second display control module which lists the link character strings included in the displayed first content and displays them together with the first content, a selection module which selects, according to a user operation, a link character string displayed, and a third display control module which displays content on an item stored in such a manner that the item is linked to the selected link character string.

Abstract: A information display apparatus includes a content storage module, a controller, a specification module, and a marker information storage module. The controller controls a text to be displayed. The specification module specifies, based on a user's operation, a character string, as a marker display character string in the displayed text. The marker information storage module stores position information of the marker display character string within a storage region of the content storage module, and stores a stored time where the position information is stored as being related to the position information. The controller allows the text in an identifiable manner based on the position information, wherein a mode of the identifiable display is differed in accordance with time elapsed since the stored time for the marker display character string.

Abstract: [Problem to be Solved] To stably supply a fiber structure having excellent ashing durability, water/oil repellency and antifouling properties. [Solution] A fiber structure characterized in that each of the single fibers used in it is covered, on the surface thereof, with a resin film containing an organic fluorochemicals via a resin film containing a triazine ring-containing compound or containing an organic fluorochemicals and a triazine ring-containing compound, and that said fiber structure has a water repellency level of grade 4 or higher and an oil repellency level of grade 4 or higher after 20 times of washing.

Abstract: Subarrays, which constitute a memory cell array, each include a bit line driving transistor having a drain connected to a bit line, a source is connected to an interconnection having a power supply potential, and a gate is connected to a sub-bit line. The plurality of memory cells are each provided in such away that a gate is connected to a word line, a source is grounded, and whether a drain is connected to the sub-bit line or not is selected in correspondence to data to be stored. Transmission transistors each have a gate connected to the bit line, a source connected to a loading transistor section, and a drain connected to the sub-bit line.

Abstract: Subarrays, which constitute a memory cell array, each include a bit line driving transistor having a drain connected to a bit line, a source is connected to an interconnection having a power supply potential, and a gate is connected to a sub-bit line. The plurality of memory cells are each provided in such away that a gate is connected to a word line, a source is grounded, and whether a drain is connected to the sub-bit line or not is selected in correspondence to data to be stored. Transmission transistors each have a gate connected to the bit line, a source connected to a loading transistor section, and a drain connected to the sub-bit line.

Abstract: A circuit on an end column of a divided memory array is formed by a block selection transistor having the same shape as that of a memory cell transistor. As the pattern of the connecting section between the main bit line and the sub-bit line is made in the same shape as that of the memory cell, it is possible to realize a pattern uniformity and to eliminate the need for using memory array dummy patterns.

Abstract: Subarrays, which constitute a memory cell array, each include a bit line driving transistor having a drain connected to a bit line, a source is connected to an interconnection having a power supply potential, and a gate is connected to a sub-bit line. The plurality of memory cells are each provided in such away that a gate is connected to a word line, a source is grounded, and whether a drain is connected to the sub-bit line or not is selected in correspondence to data to be stored. Transmission transistors each have a gate connected to the bit line, a source connected to a loading transistor section, and a drain connected to the sub-bit line.

Abstract: Subarrays, which constitute a memory cell array, each include a bit line driving transistor having a drain connected to a bit line, a source is connected to an interconnection having a power supply potential, and a gate is connected to a sub-bit line. The plurality of memory cells are each provided in such away that a gate is connected to a word line, a source is grounded, and whether a drain is connected to the sub-bit line or not is selected in correspondence to data to be stored. Transmission transistors each have a gate connected to the bit line, a source connected to a loading transistor section, and a drain connected to the sub-bit line.

Abstract: Subarrays, which constitute a memory cell array, each include a bit line driving transistor having a drain connected to a bit line, a source is connected to an interconnection having a power supply potential, and a gate is connected to a sub-bit line. The plurality of memory cells are each provided in such away that a gate is connected to a word line, a source is grounded, and whether a drain is connected to the sub-bit line or not is selected in correspondence to data to be stored. Transmission transistors each have a gate connected to the bit line, a source connected to a loading transistor section, and a drain connected to the sub-bit line.

Abstract: A semiconductor memory device includes a memory cell array, a charge circuit which compensates for OFF leakage current developed at selected bit lines, a reset circuit having a ground potential corresponding to a potential at non-selected bit lines, a read circuit constituted by a plurality of transistors whose gates are connected to the bit lines, and a bit line precharge circuit which charges the selected bit lines for a fixed time period. As a result of adopting such a configuration, there is no need to provide a transmission gate, such as a column decoder, to a charging path between the read circuit and the bit lines, so that a low-power supply voltage operation can be effected without the influence of a substrate bias effect.

Abstract: A semiconductor memory device comprising multiple memory cells, main bit lines, a sub-bit line, a differential amplifier circuit, a precharge circuit, a first control circuit generating first and second control signals, and a second control circuit generating third and fourth control signals, wherein the differential amplifier circuit amplifies the voltage difference between the sub-bit line and the main bit line according to the first and second control signals; the precharge circuit charges the sub-bit line and the main bit line to a first voltage when the third and fourth control signals are activated and charges only the sub-bit line when the third and fourth control signals are inactivated, whereby the voltage of the main bit line is set so as to be lower than the voltage of the sub-bit line, and both the stabilization of reading operation and the increase in capacity are attained.

Abstract: A semiconductor memory device includes a memory cell array, a charge circuit which compensates for OFF leakage current developed at selected bit lines, a reset circuit having a ground potential corresponding to a potential at non-selected bit lines, a read circuit constituted by a plurality of transistors whose gates are connected to the bit lines, and a bit line precharge circuit which charges the selected bit lines for a fixed time period. As a result of adopting such a configuration, there is no need to provide a transmission gate, such as a column decoder, to a charging path between the read circuit and the bit lines, so that a low-power supply voltage operation can be effected without the influence of a substrate bias effect.

Abstract: In semiconductor memory devices having hierarchical bit line structures, a transfer transistor provided between a main bit line and a sub-bit line hinders achievement of a high speed and a low voltage. A sub-bit line SBL in a subarray 12 is connected via a first transistor PC1 to a power source voltage, and via a second transistor NC1 to a ground voltage. A main bit line MBLj is connected via a third transistor PD1 to the power source voltage. The gate electrodes of the first transistor PC1 and the second transistor NC1 are connected to the main bit line MBLj, the gate electrode of the third transistor PD1 is connected to the sub-bit line SBL. In an initial state, a voltage of the main bit line MBLj is controlled to be at an H level, and voltages of word lines WLi1 to Wlip are controlled to be at an L level. When a read operation is performed, the voltage of the main bit line MBLj transitions to the L level, and thereafter, the voltage of a selected word line transitions to the H level.