Patents by Inventor Wataru Futo
Wataru Futo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7151025Abstract: A method of manufacturing a semiconductor device on a semiconductor substrate having a first region and a second region. This method beings by forming a transistor in the first region of said semiconductor substrate. This transistor includes a pair of impurity diffusion regions and a gate electrode. Then forming a first insulating film over the first and second regions with this first insulating film covering the transistor in the first region. Thereafter, patterning the first insulating film to selectively remove the first insulating film in the second region. Then forming a second insulating film over the first and second regions. Thereafter, forming at least one contact hole through the second and first insulating film. The contact hole reaches one of the impurity diffusion regions. Finally, forming a conductive layer in the contact hole.Type: GrantFiled: March 17, 2003Date of Patent: December 19, 2006Assignee: Fujitsu LimitedInventors: Kazuo Itabashi, Osamu Tsuboi, Yuji Yokoyama, Kenichi Inoue, Koichi Hashimoto, Wataru Futo
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Patent number: 6936510Abstract: A semiconductor memory device comprising: a first insulating film covering the upper and side surfaces of a gate electrode; a second insulating film formed on the substrate covering the first insulating film; a pair of contact holes formed through the second insulating film and reaching the impurity diffusion regions; a conductive plug embedded in one of the contact holes; a third insulating film formed on the second insulating film covering the conductive plug, and having a first aperture on the other contact hole; a bit line formed on the third insulating film and connected to the other impurity diffusion region through the first aperture and the other contact hole; a fourth insulating film covering the upper and side surfaces of the bit line; a second aperture formed through the third insulating film in alignment with the fourth insulating film covering the side surface of the bit line; a storage electrode formed to extend over the bit line, insulated from the bit line by the third and fourth insulating fiType: GrantFiled: March 17, 2003Date of Patent: August 30, 2005Assignee: Fujitsu LimitedInventors: Kazuo Itabashi, Osamu Tsuboi, Yuji Yokoyama, Kenichi Inoue, Koichi Hashimoto, Wataru Futo
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Patent number: 6620674Abstract: A semiconductor memory device comprising: a first insulating film covering the upper and side surfaces of a gate electrode; a second insulating film formed on the substrate covering the first insulating film; a pair of contact holes formed through the second insulating film and reaching the impurity diffusion regions; a conductive plug embedded in one of the contact holes; a third insulating film formed on the second insulating film covering the conductive plug, and having a first aperture on the other contact hole; a bit line formed on the third insulating film and connected to the other impurity diffusion region through the first aperture and the other contact hole; a fourth insulating film covering the upper and side surfaces of the bit line; a second aperture formed through the third insulating film in alignment with the fourth insulating film covering the side surface of the bit line; a storage electrode formed to extend over the bit line, insulated from the bit line by the third and fourth insulating fiType: GrantFiled: August 15, 2000Date of Patent: September 16, 2003Assignee: Fujitsu LimitedInventors: Kazuo Itabashi, Osamu Tsuboi, Yuji Yokoyama, Kenichi Inoue, Koichi Hashimoto, Wataru Futo
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Publication number: 20030168676Abstract: A semiconductor memory device comprising: a first insulating film covering the upper and side surfaces of a gate electrode; a second insulating film formed on the substrate covering the first insulating film; a pair of contact holes formed through the second insulating film and reaching the impurity diffusion regions; a conductive plug embedded in one of the contact holes; a third insulating film formed on the second insulating film covering the conductive plug, and having a first aperture on the other contact hole; a bit line formed on the third insulating film and connected to the other impurity diffusion region through the first aperture and the other contact hole; a fourth insulating film covering the upper and side surfaces of the bit line; a second aperture formed through the third insulating film in alignment with the fourth insulating film covering the side surface of the bit line; a storage electrode formed to extend over the bit line, insulated from the bit line by the third and fourth insulating fiType: ApplicationFiled: March 17, 2003Publication date: September 11, 2003Applicant: FUJITSU LIMITEDInventors: Kazuo Itabashi, Osamu Tsuboi, Yuji Yokoyama, Kenichi Inoue, Koichi Hashimoto, Wataru Futo
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Publication number: 20030160271Abstract: A semiconductor memory device comprising: a first insulating film covering the upper and side surfaces of a gate electrode; a second insulating film formed on the substrate covering the first insulating film; a pair of contact holes formed through the second insulating film and reaching the impurity diffusion regions; a conductive plug embedded in one of the contact holes; a third insulating film formed on the second insulating film covering the conductive plug, and having a first aperture on the other contact hole; a bit line formed on the third insulating film and connected to the other impurity diffusion region through the first aperture and the other contact hole; a fourth insulating film covering the upper and side surfaces of the bit line; a second aperture formed through the third insulating film in alignment with the fourth insulating film covering the side surface of the bit line; a storage electrode formed to extend over the bit line, insulated from the bit line by the third and fourth insulating fiType: ApplicationFiled: March 17, 2003Publication date: August 28, 2003Applicant: FUJITSU LIMITEDInventors: Kazuo Itabashi, Osamu Tsuboi, Yuji Yokoyama, Kenichi Inoue, Koichi Hashimoto, Wataru Futo
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Patent number: 6440844Abstract: The method of manufacturing a semiconductor device includes the steps of forming copper wiring; reducing an oxide film on the surface of the copper wiring by heating the copper wiring to a temperature in a range of 250° C.-450° C. under reductive gas or by treating the copper wiring in plasma of reductive gas; and then forming a film of a material not containing oxygen on the copper wiring without exposing the copper wiring to external atmosphere, and can provide a semiconductor device with good copper wiring.Type: GrantFiled: July 8, 1998Date of Patent: August 27, 2002Assignee: Fujitsu LimitedInventors: Hideo Takagi, Kiyoshi Izumi, Wataru Futo, Satoshi Otsuka, Shigetaka Uji, Masataka Hoshino, Yukihiro Satoh, Koji Endo, Yuzuru Ohta, Nobuhiro Misawa
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Publication number: 20020027287Abstract: To reduce the connection resistance between copper wirings, and to improve the reliability of the wiring such as anti-electromigration characteristics.Type: ApplicationFiled: July 8, 1998Publication date: March 7, 2002Applicant: FUJITSU LIMITEDInventors: HIDEO TAKAGI, KIYOSHI IZUMI, WATARU FUTO, SATOSHI OTSUKA, SHIGETAKA UJI, MASATAKA HOSHINO, YUKIHIRO SATOH, KOJI ENDO, YUZURU OHTA, NOBUHIRO MISAWA
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Patent number: 6285045Abstract: A semiconductor memory device comprising: a first insulating film covering the upper and side surfaces of a gate electrode; a second insulating film formed on the substrate covering the first insulating film; a pair of contact holes formed through the second insulating film and reaching the impurity diffusion regions; a conductive plug embedded in one of the contact holes; a third insulating film formed on the second insulating film covering the conductive plug, and having a first aperture on the other contact hole; a bit line formed on the third insulating film and connected to the other impurity diffusion region through the first aperture and the other contact hole; a fourth insulating film covering the upper and side surfaces of the bit line; a second aperture formed through the third insulating film in alignment with the fourth insulating film covering the side surface of the bit line; a storage electrode formed to extend over the bit line, insulated from the bit line by the third and fourth insulating fiType: GrantFiled: July 10, 1997Date of Patent: September 4, 2001Assignee: Fujitsu LimitedInventors: Kazuo Itabashi, Osamu Tsuboi, Yuji Yokoyama, Kenichi Inoue, Koichi Hashimoto, Wataru Futo
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Patent number: 6174796Abstract: A semiconductor device manufacturing method having a copper wiring, comprises the steps of forming a second insulating film for covering the wiring on a first insulating film, forming a third insulating film which is made of material different from the second insulating film on the second insulating film, coating a resist on the third insulating film and then forming an opening over the wiring by exposing and developing the resist, forming a hole or groove in the third insulating film by etching the third insulating film via the opening, removing the resist by placing the semiconductor substrate in a plasma atmosphere containing oxygen in a chamber and simultaneously removing a part of the second insulating film via the hole or groove to expose the wiring via the hole or groove, and forming a metal film in the hole or groove.Type: GrantFiled: December 30, 1998Date of Patent: January 16, 2001Assignee: Fujitsu LimitedInventors: Hideo Takagi, Wataru Futo
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Patent number: 6130482Abstract: The present invention relates to a metallization technique of a semiconductor device, more specifically to a semiconductor device having a wiring or plug of a suitable structure for high integration and a method for fabrication of the semiconductor device. The semiconductor device comprises a base substrate 10; an inter-layer insulation film 20 including a first insulation film 16 formed on the base substrate and a second insulation film 18 formed on the base substrate, and having a contact hole 22 which reaches the base substrate 10; and a conducting film 24 formed on an inside wall and a bottom of the contact hole 22, a width of the contact hole in the first insulation film 16 being larger than a width of the contact hole 22 in the second insulation film 18. The conducting film 24 on the inside wall of the contact hole 22, and the conducting film 24 on the bottom of the contact hole 22 is uninterrupted on a boundary.Type: GrantFiled: September 26, 1996Date of Patent: October 10, 2000Assignee: Fujitsu LimitedInventors: Hiroki Iio, Koichi Hashimoto, Wataru Futo
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Patent number: 5932901Abstract: A semiconductor memory device comprising: a first insulating film covering the upper and side surfaces of a gate electrode; a second insulating film formed on the substrate covering the first insulating film; a pair of contact holes formed through the second insulating film and reaching the impurity diffusion regions; a conductive plug embedded in one of the contact holes; a third insulating film formed on the second insulating film covering the conductive plug, and having a first aperture on the other contact hole; a bit line formed on the third insulating film and connected to the other impurity diffusion region through the first aperture and the other contact hole; a fourth insulating film covering the upper and side surfaces of the bit line; a second aperture formed through the third insulating film in alignment with the fourth insulating film covering the side surface of the bit line; a storage electrode formed to extend over the bit line, insulated from the bit line by the third and fourth insulating fiType: GrantFiled: July 10, 1997Date of Patent: August 3, 1999Assignee: Fujitsu LimitedInventors: Kazuo Itabashi, Osamu Tsuboi, Yuji Yokoyama, Kenichi Inoue, Koichi Hashimoto, Wataru Futo