Abstract: This invention relates to a memory device and the like that are preferably applied to a case where motion vector is detected using a block matching. Pixel data of a first frame (a reference frame) is stored in a unit A of memory cell array portion 20a in straight binary format. Pixel data of a second frame (a search frame) is stored in a unit B of memory cell array portion 20b in two's complement format. The units A and B have a plurality of memory cells, respectively. Word lines WL related to the pixel data of the first and second frames are simultaneously activated so that charges accumulated in capacitors of each of the memory cells can be combined along one bit line BL. A/D converter 53 outputs a digital signal (absolute difference value) having a value that corresponds to a total amount of charges. When reading the pixel data, a subtraction and a conversion into the absolute difference value are simultaneously performed.

Abstract: A luminance signal Ya and a color-difference signal Ua/Va constituting an input image signal is transferred to a frame memory (first memory) in the unit of line synchronously with its horizontal synchronous signal and written therein. A memory TG211 reads out a read-out request RRQ. The cycle of this request RRQ is a time computed based on a single vertical effective period of an output image signal Sc and the number of lines objective for rate conversion of an input image signal Sa. The luminance signal Ya and color-difference signal Ua/Va are transferred in the unit of line from the frame memory to rate conversion units (second memory) through buffers. There occurs no deflection in this transfer cycle and in each transfer cycle, the stable data transmission band can be secured.

Abstract: An information signal processor that is well suitable for use in conversion of an SD signal into an HD signal. The pixel data set corresponding to an objective position in the HD signal is extracted selectively from the SD signal. Class CL to which pixel data set of the objective position belongs is then obtained using the pixel data set. A coefficient production circuit produces coefficient data sets Wi for each class based on coefficient seed data sets and values of picture quality adjusting parameters h and v. A tap selection circuit selectively extracts the data sets xi from the SD signal and then, a calculation circuit produces the pixel data sets of the objective position in the HD signal using the data sets xi and the coefficient data sets Wi. It is thus possible to save on the storage capacity of the memory.

Abstract: An apparatus for use in conversion of an SD signal into an HD signal. The pixel data sets of a tap corresponding to an objective position in the HD signal are extracted selectively from the SD signal. Class CL to which pixel data set of the objective position belongs is then obtained using the pixel data sets of the tap. A coefficient production circuit produces coefficient data sets Wi for each class based on coefficient seed data sets for each class and values of picture quality adjusting parameters, h and v obtained by user operation. A tap selection circuit selectively extracts the data sets xi of the tap corresponding to the objective position in the HD signal from the SD signal and then, a calculation circuit produces the pixel data sets of the objective position in the HD signal according to an estimation equation using the data sets xi and the coefficient data sets Wi corresponding to the class CL read out of a memory.

Abstract: An information signal processor that is well suitable for use in conversion of an SD signal into an HD signal. The pixel data set corresponding to an objective position in the HD signal is extracted selectively from the SD signal. Class CL to which pixel data set of the objective position belongs is then obtained using the pixel data set. A coefficient production circuit produces coefficient data sets Wi for each class based on coefficient seed data sets and values of picture quality adjusting parameters h and v. A tap selection circuit selectively extracts the data sets xi from the SD signal and then, a calculation circuit produces the pixel data sets of the objective position in the HD signal using the data sets xi and the coefficient data sets Wi. It is thus possible to save on the storage capacity of the memory.

Abstract: This invention relates to a memory device and the like that are preferably applied to a case where motion vector is detected using a block matching. Pixel data of a first frame (a reference frame) is stored in a unit A of memory cell array portion 20a in straight binary format. Pixel data of a second frame (a search frame) is stored in a unit B of memory cell array portion 20b in two's complement format. The units A and B have a plurality of memory cells, respectively. Word lines WL related to the pixel data of the first and second frames are simultaneously activated so that charges accumulated in capacitors of each of the memory cells can be combined along one bit line BL. A/D converter 53 outputs a digital signal (absolute difference value) having a value that corresponds to a total amount of charges. When reading the pixel data, a subtraction and a conversion into the absolute difference value are simultaneously performed.

Abstract: This invention relates to a memory device and the like that are preferably applied to a case where motion vector is detected using a block matching. Pixel data of a first frame (a reference frame) is stored in a unit A of memory cell array portion 20a in straight binary format. Pixel data of a second frame (a search frame) is stored in a unit B of memory cell array portion 20b in two's complement format. The units A and B have a plurality of memory cells, respectively. Word lines WL related to the pixel data of the first and second frames are simultaneously activated so that charges accumulated in capacitors of each of the memory cells can be combined along one bit line BL. A/D converter 53 outputs a digital signal (absolute difference value) having a value that corresponds to a total amount of charges. When reading the pixel data, a subtraction and a conversion into the absolute difference value are simultaneously performed.

Abstract: The present invention relates to an information signal processor and the like preferable for use in the case of converting a format of an image signal or converting an image size. An input image signal Vin (525i signal) is converted into an output image signal Vout (such as 1080i signal, XGA signal, or 525i signal for obtaining an image to be displayed in a different magnification). A class code CL is obtained from tap data selectively extracted from the Vin and corresponding to each pixel (pixel at a target position) within a unit pixel block, which constitutes Vout. A coefficient production circuit 136 produces coefficient data for each class, which is used at the time of calculating the pixel data at the target position, based on the coefficient seed data for each class and position information h, v about the target position generated in a position information generation circuit 139.

Abstract: A picture information converting apparatus for generating a plurality of output picture signals.

Abstract: The invention relates to an information signal processor, etc. that are well suitable for use in conversion of, for example, an SD signal into an HD signal. The pixel data sets of a tap corresponding to an objective position in the HD signal are extracted selectively from the SD signal. Class CL to which pixel data set of the objective position belongs is then obtained using the pixel data sets of the tap. A coefficient production circuit (136) produces coefficient data sets Wi for each class based on coefficient seed data sets for each class and values of picture quality adjusting parameters, h and v obtained by user operation.

Abstract: The invention relates to an information signal processor suitable for use in conversion of, for example, an SD signal. Pixel data sets are extracted selectively from the SD signal. Class CL is then obtained using the pixel data sets. A coefficient production circuit produces coefficient data sets Wi for each class based on coefficient seed data sets for each class and values of picture quality adjusting parameters, h and v obtained by user operation. A tap selection circuit selectively extracts the data sets xi of the tap corresponding to the objective position in the HD signal from the SD signal and then, a calculation circuit produces the pixel data sets of the objective position in the HD signal according to an estimation equation using the data sets xi and the coefficient data sets Wi.

Abstract: An information signal processor that is well suitable for use in conversion of an SD signal into an HD signal. The pixel data set corresponding to an objective position in the HD signal is extracted selectively from the SD signal. Class CL to which pixel data set of the objective position belongs is then obtained using the pixel data set. A coefficient production circuit produces coefficient data sets Wi for each class based on coefficient seed data sets and values of picture quality adjusting parameters h and v. A tap selection circuit selectively extracts the data sets xi from the SD signal and then, a calculation circuit produces the pixel data sets of the objective position in the HD signal using the data sets xi and the coefficient data sets Wi. It is thus possible to save on the storage capacity of the memory.

Abstract: An information signal processor that is well suitable for use in conversion of an SD signal into an HD signal. The pixel data set corresponding to an objective position in the HD signal is extracted selectively from the SD signal. Class CL to which pixel data set of the objective position belongs is then obtained using the pixel data set. A coefficient production circuit produces coefficient data sets Wi for each class based on coefficient seed data sets and values of picture quality adjusting parameters h and v. A tap selection circuit selectively extracts the data sets xi from the SD signal and then, a calculation circuit produces the pixel data sets of the objective position in the HD signal using the data sets xi and the coefficient data sets Wi . It is thus possible to save on the storage capacity of the memory.

Abstract: An information signal processor that is well suitable for use in conversion of an SD signal into an HD signal. The pixel data set corresponding to an objective position in the HD signal is extracted selectively from the SD signal. Class CL to which pixel data set of the objective position belongs is then obtained using the pixel data set. A coefficient production circuit produces coefficient data sets Wi for each class based on coefficient seed data sets and values of picture quality adjusting parameters h and v. A tap selection circuit selectively extracts the data sets xi from the SD signal and then, a calculation circuit produces the pixel data sets of the objective position in the HD signal using the data sets xi and the coefficient data sets Wi. It is thus possible to save on the storage capacity of the memory.

Abstract: A 525i (interlace) signal can be converted into a 1050i signal or a 525p (progressive) signal. A calculating circuit generates pixels of an output picture signal with a linear estimation expression of predictive taps received from a tap selecting circuit and a coefficient received from a coefficient memory. The coefficient memory stores coefficients pre-obtained for individual classes. A class is determined by combining a spatial class corresponding to spatial class taps received from a tap selecting circuit and motion class taps received from a tap selecting circuit. A line sequential converting circuit converts a scanning line structure of an output signal of the calculating circuit 34 and obtains an output picture signal. The output picture signal is designated with a conversion method selection signal. Information corresponding to the selection signal is loaded from an information memory bank to the coefficient memory and registers.

Abstract: The present invention relates to an information signal processor and the like preferable for use in the case where a SD signal is converted into a HD signal. A space class and a movement class are detected from the tap pixel data, which is selectively extracted from the SD signal, correspond to a target position in the HD signal. In a memory bank 135, a coefficient seed data in each class and term selection information are stored. In the coefficient production circuit 136, coefficient data Wi in each class is produced according to a production equation containing the term selected by term selection information, using the coefficient seed data in each class and the values of parameters h, v for image adjustment. In a calculation circuit 127, pixel data at the target position in the HD signal is obtained from the prediction tap data xi and the coefficient data Wi, by use of an estimated equation.

Abstract: The present invention relates to an information signal processor and the like preferable for use in the case of converting a format of an image signal or converting an image size. An input image signal, Vin, is converted into an output image signal, Vout that has different format and/or size therefrom. A class code, CL, is obtained from tap data extracted from the Vin and corresponding to each pixel (pixel at a target position) within a unit pixel block, which constitutes Vout.

Abstract: The present invention relates to an information signal processor and the like preferable for use in the case of converting a format of an image signal or converting an image size. An input image signal Vin (525i signal) is converted into an output image signal Vout (such as 1080i signal, XGA signal, or 525i signal for obtaining an image to be displayed in a different magnification). A class code CL is obtained from tap data selectively extracted from the Vin and corresponding to each pixel (pixel at a target position) within a unit pixel block, which constitutes Vout. A coefficient production circuit produces coefficient data for each class, which is used at the time of calculating the pixel data at the target position, based on the coefficient seed data for each class and position information h, v about the target position generated in a position information generation circuit.

Abstract: This invention relates to a memory device and the like that are preferably applied to a case where motion vector is detected using a block matching. Pixel data of a first frame (a reference frame) is stored in a unit A of memory cell array portion 20a in straight binary format. Pixel data of a second frame (a search frame) is stored in a unit B of memory cell array portion 20b in two's complement format. The units A and B have a plurality of memory cells, respectively. Word lines WL related to the pixel data of the first and second frames are simultaneously activated so that charges accumulated in capacitors of each of the memory cells can be combined along one bit line BL. A/D converter 53 outputs a digital signal (absolute difference value) having a value that corresponds to a total amount of charges. When reading the pixel data, a subtraction and a conversion into the absolute difference value are simultaneously performed.

Abstract: The present invention relates to an information signal processor and the like preferable for use in the case of converting a format of an image signal or converting an image size. An input image signal Vin (525i signal) is converted into an output image signal Vout (such as 1080i signal, XGA signal, or 525i signal for obtaining an image to be displayed in a different magnification). A class code CL is obtained from tap data selectively extracted from the Vin and corresponding to each pixel (pixel at a target position) within a unit pixel block, which constitutes Vout. A coefficient production circuit 136 produces coefficient data for each class, which is used at the time of calculating the pixel data at the target position, based on the coefficient seed data for each class and phase information h, v about the target position generated in a phase information generation circuit 139.