Patents by Inventor Wataru Otsuka
Wataru Otsuka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11295812Abstract: Memory devices and memory operational methods are described. One example memory system includes a common conductor and a plurality of memory cells coupled with the common conductor. The memory system additionally includes access circuitry configured to provide different ones of the memory cells into one of a plurality of different memory states at a plurality of different moments in time between first and second moments in time. The access circuitry is further configured to maintain the common conductor at a voltage potential, which corresponds to the one memory state, between the first and second moments in time to provide the memory cells into the one memory state.Type: GrantFiled: June 26, 2019Date of Patent: April 5, 2022Assignee: Micron Technology, Inc.Inventors: Wataru Otsuka, Takafumi Kunihiro, Tomohito Tsushima, Makoto Kitagawa, Jun Sumino
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Patent number: 10783961Abstract: Memory cells, memory systems and methods are described. In one embodiment, a memory cell includes electrodes and a memory element, and a first electrically conductive structure is formed within dielectric material providing the memory element in a low resistance state as a result of a first voltage of a first polarity being applied across the electrodes. Additionally, the first electrically conductive structure is removed from the dielectric material providing the memory element in a high resistance state as a result of a second voltage of a second polarity, which is opposite to the first polarity, being applied across the electrodes. A permanent and irreversible electrically conductive structure is formed within the dielectric material providing the memory element in the low resistance state as a result of a third voltage of the second polarity and having an increased potential compared with the second voltage being applied across the electrodes.Type: GrantFiled: June 11, 2019Date of Patent: September 22, 2020Assignee: Micron Technology, Inc.Inventors: Wataru Otsuka, Takafumi Kunihiro, Tomohito Tsushima, Makoto Kitagawa, Jun Sumino, D. V. Nirmal Ramaswamy
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Patent number: 10622067Abstract: Memory devices and memory operational methods are described. One example memory system includes a common conductor and a plurality of memory cells coupled with the common conductor. The memory system additionally includes access circuitry configured to provide different ones of the memory cells into one of a plurality of different memory states at a plurality of different moments in time between first and second moments in time. The access circuitry is further configured to maintain the common conductor at a voltage potential, which corresponds to the one memory state, between the first and second moments in time to provide the memory cells into the one memory state.Type: GrantFiled: November 13, 2018Date of Patent: April 14, 2020Assignee: Micron Technology, Inc.Inventors: Wataru Otsuka, Takafumi Kunihiro, Tomohito Tsushima, Makoto Kitagawa, Jun Sumino
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Patent number: 10492794Abstract: According to the present invention, there is provided a clip cartridge in which a clip having a structure enabling a user to easily perform a series of procedures can be easily and reliably mounted on a treatment instrument body. A clip cartridge (200) according to the present invention includes an inner case (30) that has a first accommodation region (32) for accommodating a clip (110), and an outer case (40) that has an elongated insertion hole (43) into which a treatment instrument body (90) is inserted, and a second accommodation region (42) which accommodates the inner case (30) so as to be movable. The treatment instrument body (90) is inserted into the insertion hole (43), and an operation wire is pressed forward so that a distal connection portion and a diameter enlargement portion of the sleeve protrude from the sheath to a distal side and enter the second accommodation region (42), and so that a diameter enlargement portion is elastically enlarged in diameter.Type: GrantFiled: February 23, 2017Date of Patent: December 3, 2019Assignee: SUMITOMO BAKELITE CO., LTD.Inventors: Masao Ikeda, Takuya Hayashi, Etsuro Yamabe, Hideaki Matsunami, Wataru Otsuka, Tetsuro Abe
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Publication number: 20190318782Abstract: Memory devices and memory operational methods are described. One example memory system includes a common conductor and a plurality of memory cells coupled with the common conductor. The memory system additionally includes access circuitry configured to provide different ones of the memory cells into one of a plurality of different memory states at a plurality of different moments in time between first and second moments in time. The access circuitry is further configured to maintain the common conductor at a voltage potential, which corresponds to the one memory state, between the first and second moments in time to provide the memory cells into the one memory state.Type: ApplicationFiled: June 26, 2019Publication date: October 17, 2019Applicant: Micron Technology, Inc.Inventors: Wataru Otsuka, Takafumi Kunihiro, Tomohito Tsushima, Makoto Kitagawa, Jun Sumino
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Publication number: 20190311767Abstract: Memory cells, memory systems and methods are described. In one embodiment, a memory cell includes electrodes and a memory element, and a first electrically conductive structure is formed within dielectric material providing the memory element in a low resistance state as a result of a first voltage of a first polarity being applied across the electrodes. Additionally, the first electrically conductive structure is removed from the dielectric material providing the memory element in a high resistance state as a result of a second voltage of a second polarity, which is opposite to the first polarity, being applied across the electrodes. A permanent and irreversible electrically conductive structure is formed within the dielectric material providing the memory element in the low resistance state as a result of a third voltage of the second polarity and having an increased potential compared with the second voltage being applied across the electrodes.Type: ApplicationFiled: June 11, 2019Publication date: October 10, 2019Applicant: Micron Technology, Inc.Inventors: Wataru Otsuka, Takafumi Kunihiro, Tomohito Tsushima, Makoto Kitagawa, Jun Sumino, D. V. Nirmal Ramaswamy
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Patent number: 10438661Abstract: Memory devices and memory operational methods are described. One example memory system includes a common conductor and a plurality of memory cells coupled with the common conductor. The memory system additionally includes access circuitry configured to provide different ones of the memory cells into one of a plurality of different memory states at a plurality of different moments in time between first and second moments in time. The access circuitry is further configured to maintain the common conductor at a voltage potential, which corresponds to the one memory state, between the first and second moments in time to provide the memory cells into the one memory state.Type: GrantFiled: May 23, 2016Date of Patent: October 8, 2019Assignee: Micron Technology, Inc.Inventors: Wataru Otsuka, Takafumi Kunihiro, Tomohito Tsushima, Makoto Kitagawa, Jun Sumino
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Patent number: 10395731Abstract: Memory cells, memory systems and methods are described. In one embodiment, a memory cell includes electrodes and a memory element, and a first electrically conductive structure is formed within dielectric material providing the memory element in a low resistance state as a result of a first voltage of a first polarity being applied across the electrodes. Additionally, the first electrically conductive structure is removed from the dielectric material providing the memory element in a high resistance state as a result of a second voltage of a second polarity, which is opposite to the first polarity, being applied across the electrodes. A permanent and irreversible electrically conductive structure is formed within the dielectric material providing the memory element in the low resistance state as a result of a third voltage of the second polarity and having an increased potential compared with the second voltage being applied across the electrodes.Type: GrantFiled: December 29, 2017Date of Patent: August 27, 2019Assignee: Micron Technology, Inc.Inventors: Wataru Otsuka, Takafumi Kunihiro, Tomohito Tsushima, Makoto Kitagawa, Jun Sumino, D. V. Nirmal Ramaswamy
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Patent number: 10249366Abstract: An integrated circuit system, and a method of manufacture thereof, including: an integrated circuit die; a non-volatile memory cell in the integrated circuit die and having a bit line for reading a data condition state of the non-volatile memory cell; and a voltage clamp in the integrated circuit die, the voltage clamp having a semiconductor switch connected to the bit line for reducing voltage excursions on the bit line.Type: GrantFiled: November 18, 2016Date of Patent: April 2, 2019Assignee: Sony Semiconductor Solutions CorporationInventors: Makoto Kitagawa, Tomohito Tsushima, Wataru Otsuka, Takafumi Kunihiro
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Publication number: 20190080759Abstract: Memory devices and memory operational methods are described. One example memory system includes a common conductor and a plurality of memory cells coupled with the common conductor. The memory system additionally includes access circuitry configured to provide different ones of the memory cells into one of a plurality of different memory states at a plurality of different moments in time between first and second moments in time. The access circuitry is further configured to maintain the common conductor at a voltage potential, which corresponds to the one memory state, between the first and second moments in time to provide the memory cells into the one memory state.Type: ApplicationFiled: November 13, 2018Publication date: March 14, 2019Applicant: Micron Technology, Inc.Inventors: Wataru Otsuka, Takafumi Kunihiro, Tomohito Tsushima, Makoto Kitagawa, Jun Sumino
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Patent number: 10213251Abstract: The high-frequency treatment tool includes a flexible tube inserted into a body cavity; an operating wire inserted through the flexible tube to be movable back and forth; a treatment part arranged on a distal end of the operating wire and treats biological tissue by applying a high-frequency current; a main body that fixes a base end of the flexible tube; a slider-fixing part that fixes a base end of the operating wire guided from the base end of the flexible tube and slides the operating wire in an axis direction with respect to the main body; and a slider-zipping part provided to encircle at least a portion of an outer peripheral surface of the slider-fixing part and slides the slider-fixing part by the operation of a user. The slider-fixing part is unrotatably coupled to the main body and the slider-gripping part is rotatably coupled to the slider-fixing part.Type: GrantFiled: May 30, 2014Date of Patent: February 26, 2019Assignee: SUMITOMO BAKELITE COMPANY LIMITEDInventors: Wataru Otsuka, Shinetsu Harata
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Publication number: 20190046205Abstract: According to the present invention, there is provided a clip cartridge in which a clip having a structure enabling a user to easily perform a series of procedures can be easily and reliably mounted on a treatment instrument body. A clip cartridge (200) according to the present invention includes an inner case (30) that has a first accommodation region (32) for accommodating a clip (110), and an outer case (40) that has an elongated insertion hole (43) into which a treatment instrument body (90) is inserted, and a second accommodation region (42) which accommodates the inner case (30) so as to be movable. The treatment instrument body (90) is inserted into the insertion hole (43), and an operation wire is pressed forward so that a distal connection portion and a diameter enlargement portion of the sleeve protrude from the sheath to a distal side and enter the second accommodation region (42), and so that a diameter enlargement portion is elastically enlarged in diameter.Type: ApplicationFiled: February 23, 2017Publication date: February 14, 2019Applicant: SUMITOMO BAKELITE CO., LTD.Inventors: Masao IKEDA, Takuya HAYASHI, Etsuro YAMABE, Hideaki MATSUNAMI, Wataru OTSUKA, Tetsuro ABE
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Publication number: 20180366188Abstract: An integrated circuit system, and a method of manufacture thereof, including: an integrated circuit die; a non-volatile memory cell in the integrated circuit die and having a bit line for reading a data condition state of the non-volatile memory cell; and a voltage clamp in the integrated circuit die, the voltage clamp having a semiconductor switch connected to the bit line for reducing voltage excursions on the bit line.Type: ApplicationFiled: November 18, 2016Publication date: December 20, 2018Inventors: Makoto Kitagawa, Tomohito Tsushima, Wataru Otsuka, Takafumi Kunihiro
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Publication number: 20180144792Abstract: Memory cells, memory systems and methods are described. In one embodiment, a memory cell includes electrodes and a memory element, and a first electrically conductive structure is formed within dielectric material providing the memory element in a low resistance state as a result of a first voltage of a first polarity being applied across the electrodes. Additionally, the first electrically conductive structure is removed from the dielectric material providing the memory element in a high resistance state as a result of a second voltage of a second polarity, which is opposite to the first polarity, being applied across the electrodes. A permanent and irreversible electrically conductive structure is formed within the dielectric material providing the memory element in the low resistance state as a result of a third voltage of the second polarity and having an increased potential compared with the second voltage being applied across the electrodes.Type: ApplicationFiled: December 29, 2017Publication date: May 24, 2018Applicant: Micron Technology, Inc.Inventors: Wataru Otsuka, Takafumi Kunihiro, Tomohito Tsushima, Makoto Kitagawa, Jun Sumino, D. V. Nirmal Ramaswamy
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Publication number: 20180144797Abstract: An integrated circuit system, and a method of manufacture thereof, including: an integrated circuit die; a non-volatile memory cell in the integrated circuit die and having a bit line for reading a data condition state of the non-volatile memory cell; and a voltage clamp in the integrated circuit die, the voltage clamp having a semiconductor switch connected to the bit line for reducing voltage excursions on the bit line.Type: ApplicationFiled: November 18, 2016Publication date: May 24, 2018Inventors: Makoto Kitagawa, Tomohito Tsushima, Wataru Otsuka, Takafumi Kunihiro
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Patent number: 9911489Abstract: Memory cells, memory systems and methods are described. In one embodiment, a memory cell includes electrodes and a memory element, and a first electrically conductive structure is formed within dielectric material providing the memory element in a low resistance state as a result of a first voltage of a first polarity being applied across the electrodes. Additionally, the first electrically conductive structure is removed from the dielectric material providing the memory element in a high resistance state as a result of a second voltage of a second polarity, which is opposite to the first polarity, being applied across the electrodes. A permanent and irreversible electrically conductive structure is formed within the dielectric material providing the memory element in the low resistance state as a result of a third voltage of the second polarity and having an increased potential compared with the second voltage being applied across the electrodes.Type: GrantFiled: March 21, 2016Date of Patent: March 6, 2018Assignee: Micron Technology, Inc.Inventors: Wataru Otsuka, Takafumi Kunihiro, Tomohito Tsushima, Makoto Kitagawa, Jun Sumino, D. V. Nirmal Ramaswamy
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Patent number: 9905300Abstract: A memory device comprising a memory array comprising a plurality of memory cells, two or more fuses coupled to the memory array, wherein each of the two or more fuses contains trim data for the memory array and a mode register for selecting one of the two or more fuses to be enabled.Type: GrantFiled: January 27, 2017Date of Patent: February 27, 2018Assignee: Sony Semiconductor Solutions CorporationInventors: Makoto Kitagawa, Takafumi Kunihiro, Wataru Otsuka, Tomohito Tsushima
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Publication number: 20170140827Abstract: A memory device comprising a memory array comprising a plurality of memory cells, two or more fuses coupled to the memory array, wherein each of the two or more fuses contains trim data for the memory array and a mode register for selecting one of the two or more fuses to be enabled.Type: ApplicationFiled: January 27, 2017Publication date: May 18, 2017Inventors: Makoto Kitagawa, Takafumi Kunihiro, Wataru Otsuka, Tomohito Tsushima
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Patent number: 9646690Abstract: A method of operation of a non-volatile memory system includes: providing a resistive storage element having a high resistance state and a low resistance state; coupling an analog multiplexer to the resistive storage element for applying a bias voltage; and switching between a verification bias and a read bias through the analog multiplexer for increasing a read margin between the high resistance state and the low resistance state.Type: GrantFiled: June 25, 2015Date of Patent: May 9, 2017Assignee: Sony Semiconductor Solutions CorporationInventors: Wataru Otsuka, Jun Sumino, Tomohito Tsushima, Makoto Kitagawa, Takafumi Kunihiro
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Patent number: 9594516Abstract: A memory device comprising a memory array comprising a plurality of memory cells, two or more fuses coupled to the memory array, wherein each of the two or more fuses contains trim data for the memory array and a mode register for selecting one of the two or more fuses to be enabled.Type: GrantFiled: February 14, 2014Date of Patent: March 14, 2017Assignee: Sony Semiconductor Solutions CorporationInventors: Makoto Kitagawa, Takafumi Kunihiro, Wataru Otsuka, Tomohito Tsushima