Abstract: Reliability of a semiconductor device is improved. The semiconductor device including a first MISFET group of a plurality of first MISFETs and a second MISFET group of a plurality of second MISFETs has a plurality of trenches each formed in a semiconductor layer and formed of an upper trench part and a lower trench part, and a plurality of gate electrodes formed inside the plurality of trenches. A thinner gate insulator is formed to the upper trench part and a thicker field insulator is formed to the lower trench part. In a trench at the outermost position in the first MISFET group and a trench at the outermost position in the second MISFET group, the gate insulator is not formed in the upper trench part, but the field insulator is formed in the upper trench part and the lower trench part.

Abstract: Reliability of a semiconductor device is improved. The semiconductor device including a first MISFET group of a plurality of first MISFETs and a second MISFET group of a plurality of second MISFETs has a plurality of trenches each formed in a semiconductor layer and formed of an upper trench part and a lower trench part, and a plurality of gate electrodes formed inside the plurality of trenches. A thinner gate insulator is formed to the upper trench part and a thicker field insulator is formed to the lower trench part. In a trench at the outermost position in the first MISFET group and a trench at the outermost position in the second MISFET group, the gate insulator is not formed in the upper trench part, but the field insulator is formed in the upper trench part and the lower trench part.

Abstract: A source electrode can be patterned well in response to the densification of a semiconductor device. A first MOS transistor element is formed in a first element region and a second MOS transistor element is formed in a second element region. A first source electrode is arranged so as to straddle a first gate electrode and cover a first source layer located on both one side and the other side in a gate length direction with the first gate electrode interposed. A second source electrode is arranged so as to straddle a second gate electrode and cover a second source layer located on both one side and the other side in the gate length direction with the second gate electrode interposed.

Abstract: A semiconductor device manufacturing method includes preparing a semiconductor substrate of a first conductivity type, forming a semiconductor layer of the first conductivity type over a main surface of the semiconductor substrate, forming a plurality of first ditches in an upper surface portion of the semiconductor layer such that the first ditches are arranged in a first direction extending along an upper surface of the semiconductor substrate, forming a plurality of second ditches in bottom surface portions of each of the first ditches such that the second ditches are arranged in a second direction perpendicular to the first direction, and covering a side wall of each of the first ditches with a first insulating film and a side wall and a bottom surface of each of the second ditches with a second insulating film thicker than the first insulating film.

Abstract: A semiconductor device manufacturing method includes preparing a semiconductor substrate of a first conductivity type, forming a semiconductor layer of the first conductivity type over a main surface of the semiconductor substrate, forming a plurality of first ditches in an upper surface portion of the semiconductor layer such that the first ditches are arranged in a first direction extending along an upper surface of the semiconductor substrate, forming a plurality of second ditches in bottom surface portions of each of the first ditches such that the second ditches are arranged in a second direction perpendicular to the first direction, and covering a side wall of each of the first ditches with a first insulating film and a side wall and a bottom surface of each of the second ditches with a second insulating film thicker than the first insulating film.

Abstract: In a vertical MOSFET in which bottom portions of each gate electrode formed in a ditch are extended toward the drain region, the on resistance is reduced while preventing voltage resistance reduction and switching speed reduction caused by a capacitance increase between the gate and drain. A vertical MOSFET includes first ditches, second ditches, and gate electrodes. The first ditches are formed in an upper surface portion of an epitaxial layer formed over a semiconductor substrate and extend in a second direction extending along a main surface of the semiconductor substrate. The second ditches are formed in bottom surface portions of each of the first ditches and are arranged in the second direction. The gate electrodes are formed in the first ditches and second ditches. The gate electrodes formed in the first ditches include lower electrodes arranged in the second direction.

Abstract: In a vertical MOSFET in which bottom portions of each gate electrode formed in a ditch are extended toward the drain region, the on resistance is reduced while preventing voltage resistance reduction and switching speed reduction caused by a capacitance increase between the gate and drain. A vertical MOSFET includes first ditches, second ditches, and gate electrodes. The first ditches are formed in an upper surface portion of an epitaxial layer formed over a semiconductor substrate and extend in a second direction extending along a main surface of the semiconductor substrate. The second ditches are formed in bottom surface portions of each of the first ditches and are arranged in the second direction. The gate electrodes are formed in the first ditches and second ditches. The gate electrodes formed in the first ditches include lower electrodes arranged in the second direction.

Abstract: A low concentration P-type impurity (LCPI) layer situated over a drain layer has an impurity concentration lower than the drain layer. An N-type impurity base layer is situated over the LCPI layer. A gate insulating film is formed on the lateral side of a trench. A bottom insulation film formed to the bottom and lower portion on the lateral side of the trench has a larger thickness than the gate insulating film. A gate electrode is filled in the trench. At a cross section in the direction of the thickness including the bottom of the trench, a profile of the P-type impurity concentration is substantially constant and the difference between the maximum and minimum values is 10% or less of the average value for the maximum and minimum values. Further, the profile has a maximal value and a minimal value situated from the maximal value to the drain layer.

Abstract: A method (and resultant structure) includes forming a semiconductor layer having plural stripe-like trenches, forming a gate electrode buried partially in each of the plural trenches, and introducing an impurity into the semiconductor layer by ion implantation after forming the gate electrode. The gate electrode has a buried portion formed in each of the trenches and a protruding portion situating above the buried portion and having a width larger than that of the buried portion. The introducing the impurity includes introducing an impurity into the semiconductor layer below the protruding portion by oblique ion implantation.

Abstract: In a semiconductor device, a gate silicon dioxide layer is formed within a trench of a semiconductor wafer. A first gate electrode is formed on a sidewall of the trench of the semiconductor wafer via the gate silicon dioxide layer. An insulating layer is formed on a bottom of the trench of the semiconductor wafer via the gate silicon dioxide layer and surrounded by the first gate electrode. The insulating layer excludes silicon dioxide and has different etching characteristics from those of silicon dioxide. A second gate electrode is buried in the trench of the semiconductor wafer, and is in contact with the first gate electrode and the insulating layer.

Abstract: A method (and resultant structure) includes forming a semiconductor layer having plural stripe-like trenches, forming a gate electrode buried partially in each of the plural trenches, and introducing an impurity into the semiconductor layer by ion implantation after forming the gate electrode. The gate electrode has a buried portion formed in each of the trenches and a protruding portion situating above the buried portion and having a width larger than that of the buried portion. The introducing the impurity includes introducing an impurity into the semiconductor layer below the protruding portion by oblique ion implantation.

Abstract: In a semiconductor device, a gate silicon dioxide layer is formed within a trench of a semiconductor wafer. A first gate electrode is formed on a sidewall of the trench of the semiconductor wafer via the gate silicon dioxide layer. An insulating layer is formed on a bottom of the trench of the semiconductor wafer via the gate silicon dioxide layer and surrounded by the first gate electrode. The insulating layer excludes silicon dioxide and has different etching characteristics from those of silicon dioxide. A second gate electrode is buried in the trench of the semiconductor wafer, and is in contact with the first gate electrode and the insulating layer.

Abstract: In a semiconductor device, a gate silicon dioxide layer is formed within a trench of a semiconductor wafer. A first gate electrode is formed on a sidewall of the trench of the semiconductor wafer via the gate silicon dioxide layer. An insulating layer is formed on a bottom of the trench of the semiconductor wafer via the gate silicon dioxide layer and surrounded by the first gate electrode. The insulating layer excludes silicon dioxide and has different etching characteristics from those of silicon dioxide. A second gate electrode is buried in the trench of the semiconductor wafer, and is in contact with the first gate electrode and the insulating layer.

Abstract: In a semiconductor device, a gate silicon dioxide layer is formed within a trench of a semiconductor wafer. A first gate electrode is formed on a sidewall of the trench of the semiconductor wafer via the gate silicon dioxide layer. An insulating layer is formed on a bottom of the trench of the semiconductor wafer via the gate silicon dioxide layer and surrounded by the first gate electrode. The insulating layer excludes silicon dioxide and has different etching characteristics from those of silicon dioxide. A second gate electrode is buried in the trench of the semiconductor wafer, and is in contact with the first gate electrode and the insulating layer.

Abstract: A vertical type MOSFET and a manufacturing method thereof, in which its drift resistance is made to be low by securing its breakdown voltage between source and drain electrodes of about 150 V being the middle class breakdown voltage and its manufacturing method is easy and its manufacturing cost is low, are provided. At a vertical type MOSFET, in which an N type high resistance drift layer is formed on an N type substrate and P type base layers are formed in designated regions of the surface of the high resistance drift layer and N type source layers are formed in the base layers and gate electrodes are formed on specified regions of the surface of the high resistance drift layer, a trench type back gate section is formed in a trench positioned at a region between the gate electrodes, by filling a insulation material in the trench.

Abstract: A vertical type MOSFET and a manufacturing method thereof, in which its drift resistance is made to be low by securing its breakdown voltage between source and drain electrodes of about 150 V being the middle class breakdown voltage and its manufacturing method is easy and its manufacturing cost is low, are provided. At a vertical type MOSFET, in which an N type high resistance drift layer is formed on an N type substrate and P type base layers are formed in designated regions of the surface of the high resistance drift layer and N type source layers are formed in the base layers and gate electrodes are formed on specified regions of the surface of the high resistance drift layer, a trench type back gate section is formed in a trench positioned at a region between the gate electrodes, by filling an insulation material in the trench. And P type impurity layers are formed in the high resistance drift layer at the region right under the trench type back gate section.

Abstract: At one of main surfaces of a silicon substrate serving as an N+type drain region is arranged an N type first high resistance drift layer. On the first high resistance drift layer is arranged an N−type second high resistance drift layer. A P− type high resistance buried layer is arranged on the surface layer of the first high resistance drift layer and the bottom layer of the second high resistance drift layer at a position right under each of a plurality of P type base regions arranged on the surface layer of the second high resistance drift layer. The thickness T1 of the first high resistance drift layer is set in such a manner that a depletion layer extending over the first high resistance drift layer reaches through the drain region at a voltage lower than a sharing voltage V1 shared by the first high resistance drift layer.

Abstract: At one of main surfaces of a silicon substrate serving as an N+type drain region is arranged an N type first high resistance drift layer. On the first high resistance drift layer is arranged an N−type second high resistance drift layer. A P− type high resistance buried layer is arranged on the surface layer of the first high resistance drift layer and the bottom layer of the second high resistance drift layer at a position right under each of a plurality of P type base regions arranged on the surface layer of the second high resistance drift layer. The thickness T1 of the first high resistance drift layer is set in such a manner that a depletion layer extending over the first high resistance drift layer reaches through the drain region at a voltage lower than a sharing voltage V1 shared by the first high resistance drift layer.

Abstract: A field relaxation region of the second conductivity type is formed between the base region and a drain electrode contact portion at which the drain region contacts with a drain electrode but distanced from both the base region and the drain electrode contact portion and the field relaxation region is also separated via the drain region from the laterally extending portion of the semiconductor isolation region to form a drain current channel region between the field relaxation region and the laterally extending portion of the semiconductor isolation region and further the field relaxation region is electrically connected via an interconnection to the source region and the vertically extending portion of the semiconductor isolation region so that the field relaxation region and the semiconductor isolation region have the same potential as the source region whereby if the lateral MOS field effect transistor is reverse-biased by a voltage, then a first space charge region is formed which extend from a first p-n