Patents by Inventor Wataru Uesugi
Wataru Uesugi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220328530Abstract: A retention circuit provided in a logic circuit enables power gating. The retention circuit includes a first terminal, a node, a capacitor, and first to third transistors. The first transistor controls electrical connection between the first terminal and an input terminal of the logic circuit. The second transistor controls electrical connection between an output terminal of the logic circuit and the node. The third transistor controls electrical connection between the node and the input terminal of the logic circuit. A gate of the first transistor is electrically connected to a gate of the second transistor. In a data retention period, the node becomes electrically floating. The voltage of the node is held by the capacitor.Type: ApplicationFiled: June 21, 2022Publication date: October 13, 2022Inventors: Wataru UESUGI, Hikaru TAMURA, Atsuo ISOBE
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Patent number: 11374023Abstract: A retention circuit provided in a logic circuit enables power gating. The retention circuit includes a first terminal, a node, a capacitor, and first to third transistors. The first transistor controls electrical connection between the first terminal and an input terminal of the logic circuit. The second transistor controls electrical connection between an output terminal of the logic circuit and the node. The third transistor controls electrical connection between the node and the input terminal of the logic circuit. A gate of the first transistor is electrically connected to a gate of the second transistor. In a data retention period, the node becomes electrically floating. The voltage of the node is held by the capacitor.Type: GrantFiled: October 29, 2020Date of Patent: June 28, 2022Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Wataru Uesugi, Hikaru Tamura, Atsuo Isobe
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Publication number: 20210074734Abstract: A retention circuit provided in a logic circuit enables power gating. The retention circuit includes a first terminal, a node, a capacitor, and first to third transistors. The first transistor controls electrical connection between the first terminal and an input terminal of the logic circuit. The second transistor controls electrical connection between an output terminal of the logic circuit and the node. The third transistor controls electrical connection between the node and the input terminal of the logic circuit. A gate of the first transistor is electrically connected to a gate of the second transistor. In a data retention period, the node becomes electrically floating. The voltage of the node is held by the capacitor.Type: ApplicationFiled: October 29, 2020Publication date: March 11, 2021Inventors: Wataru UESUGI, Hikaru TAMURA, Atsuo ISOBE
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Patent number: 10825836Abstract: A retention circuit provided in a logic circuit enables power gating. The retention circuit includes a first terminal, a node, a capacitor, and first to third transistors. The first transistor controls electrical connection between the first terminal and an input terminal of the logic circuit. The second transistor controls electrical connection between an output terminal of the logic circuit and the node. The third transistor controls electrical connection between the node and the input terminal of the logic circuit. A gate of the first transistor is electrically connected to a gate of the second transistor. In a data retention period, the node becomes electrically floating. The voltage of the node is held by the capacitor.Type: GrantFiled: October 18, 2019Date of Patent: November 3, 2020Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Wataru Uesugi, Hikaru Tamura, Atsuo Isobe
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Publication number: 20200168635Abstract: A retention circuit provided in a logic circuit enables power gating. The retention circuit includes a first terminal, a node, a capacitor, and first to third transistors. The first transistor controls electrical connection between the first terminal and an input terminal of the logic circuit. The second transistor controls electrical connection between an output terminal of the logic circuit and the node. The third transistor controls electrical connection between the node and the input terminal of the logic circuit. A gate of the first transistor is electrically connected to a gate of the second transistor. In a data retention period, the node becomes electrically floating. The voltage of the node is held by the capacitor.Type: ApplicationFiled: October 18, 2019Publication date: May 28, 2020Inventors: Wataru UESUGI, Hikaru TAMURA, Atsuo ISOBE
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Patent number: 10490258Abstract: A semiconductor device with low power consumption or a semiconductor device with a reduced area is provided. The semiconductor device includes a cell array including a first memory cell and a second memory cell; and a sense amplifier circuit including a first sense amplifier and a second sense amplifier. The cell array is over the sense amplifier circuit. The first sense amplifier is electrically connected to the first memory cell through a first wiring BL. The second sense amplifier is electrically connected to the second memory cell through a second wiring BL. The first sense amplifier and the second sense amplifier are electrically connected to a wiring GBL. The sense amplifier circuit is configured to select one of a potential of the first wiring BL and a potential of the second wiring BL and output the selected potential to the wiring GBL.Type: GrantFiled: July 10, 2017Date of Patent: November 26, 2019Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Tatsuya Onuki, Kiyoshi Kato, Wataru Uesugi, Takahiko Ishizu
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Patent number: 10453863Abstract: A retention circuit provided in a logic circuit enables power gating. The retention circuit includes a first terminal, a node, a capacitor, and first to third transistors. The first transistor controls electrical connection between the first terminal and an input terminal of the logic circuit. The second transistor controls electrical connection between an output terminal of the logic circuit and the node. The third transistor controls electrical connection between the node and the input terminal of the logic circuit. A gate of the first transistor is electrically connected to a gate of the second transistor. In a data retention period, the node becomes electrically floating. The voltage of the node is held by the capacitor.Type: GrantFiled: December 4, 2018Date of Patent: October 22, 2019Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Wataru Uesugi, Hikaru Tamura, Atsuo Isobe
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Publication number: 20190221586Abstract: A retention circuit provided in a logic circuit enables power gating. The retention circuit includes a first terminal, a node, a capacitor, and first to third transistors. The first transistor controls electrical connection between the first terminal and an input terminal of the logic circuit. The second transistor controls electrical connection between an output terminal of the logic circuit and the node. The third transistor controls electrical connection between the node and the input terminal of the logic circuit. A gate of the first transistor is electrically connected to a gate of the second transistor. In a data retention period, the node becomes electrically floating. The voltage of the node is held by the capacitor.Type: ApplicationFiled: December 4, 2018Publication date: July 18, 2019Inventors: Wataru UESUGI, Hikaru TAMURA, Atsuo ISOBE
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Patent number: 10296157Abstract: To provide a display device which includes a touch sensor and a large number of pixels and in which a driver circuit of a display portion and a driver circuit of a touch sensor are formed in one IC. The display device includes the display portion, the touch sensor, and a plurality of ICs. The plurality of ICs each include a first circuit. One of the plurality of ICs includes a second circuit and a third circuit. The first circuit has a function of outputting a video signal to the display portion. The second circuit has a function of outputting a signal for driving a sensor element included in the touch sensor. The third circuit has a function of converting an analog signal output from the sensor element into a digital signal.Type: GrantFiled: May 23, 2016Date of Patent: May 21, 2019Inventors: Kei Takahashi, Wataru Uesugi, Hiromichi Godo
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Patent number: 10236884Abstract: A semiconductor device with lower power consumption and an electronic device including the same are provided. To reduce leakage current flowing in a word line driver circuit, a switching element is provided, specifically, between the word line driver circuit and a high or low voltage power source. When there is no memory access, the switching element is turned off, thereby interrupting application of voltage (or current) from the high or low voltage power source to the word line driver circuit. Furthermore, to reduce the stand-by power due to precharge of a bit line, a switching element is provided in a bit line driver circuit, specifically, between the bit line and a high or low voltage power source. When there is no memory access, the switching element is turned off, thereby interrupting application of voltage (or current) from the high or low voltage power source to the bit line driver circuit.Type: GrantFiled: February 8, 2016Date of Patent: March 19, 2019Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Takahiko Ishizu, Wataru Uesugi
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Patent number: 10164612Abstract: The storage circuit includes first and second logic circuits, first and second transistors whose channel formation regions include an oxide semiconductor, and a capacitor. The first and second transistors are connected to each other in series, and the capacitor is connected to a connection node of the first and second transistors. The first transistor functions as a switch that controls connection between an output terminal of the first logic circuit and the capacitor. The second transistor functions as a switch that controls connection between the capacitor and an input terminal of the second logic circuit. Clock signals whose phases are inverted from each other are input to gates of the first and second transistors. Since the storage circuit has a small number of transistors and a small number of transistors controlled by the clock signals, the storage circuit is a low-power circuit.Type: GrantFiled: September 1, 2016Date of Patent: December 25, 2018Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Yukio Maehashi, Seiichi Yoneda, Wataru Uesugi
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Patent number: 10153301Abstract: A retention circuit provided in a logic circuit enables power gating. The retention circuit includes a first terminal, a node, a capacitor, and first to third transistors. The first transistor controls electrical connection between the first terminal and an input terminal of the logic circuit. The second transistor controls electrical connection between an output terminal of the logic circuit and the node. The third transistor controls electrical connection between the node and the input terminal of the logic circuit. A gate of the first transistor is electrically connected to a gate of the second transistor. In a data retention period, the node becomes electrically floating. The voltage of the node is held by the capacitor.Type: GrantFiled: July 10, 2017Date of Patent: December 11, 2018Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Wataru Uesugi, Hikaru Tamura, Atsuo Isobe
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Patent number: 10037294Abstract: A semiconductor device including a memory which can perform a pipeline operation is provided. The semiconductor device includes a processor core, a bus, and a memory section. The memory section includes a first memory. The first memory includes a plurality of local arrays. The local array includes a sense amplifier array and a local cell array stacked thereover. The local cell array is provided a memory cell including one transistor and one capacitor. The transistor is preferably an oxide semiconductor transistor. The first memory is configured to generate a wait signal. The wait signal is generated when a request for writing data to the same local array is received over two successive clock cycles from the processor core. The wait signal is sent to the processor core via the bus. The processor core stands by for a request for the memory section on the basis of the wait signal.Type: GrantFiled: May 9, 2017Date of Patent: July 31, 2018Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Tatsuya Onuki, Wataru Uesugi
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Patent number: 10033361Abstract: A level-shift circuit that operates stably is provided. The level-shift circuit has a function of boosting a first signal having an amplitude voltage between a first voltage and a second voltage to a second signal having an amplitude voltage between a third voltage and the second voltage. The level-shift circuit includes first to eighth transistors. Gates of the third and seventh transistors are electrically connected to a wiring for transmitting a third signal for controlling the amounts of current flowing into one of a source and a drain of the first transistor, one of a source and a drain of the second transistor, one of a source and a drain of the fifth transistor, and one of a source and a drain of the sixth transistor.Type: GrantFiled: December 21, 2016Date of Patent: July 24, 2018Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Wataru Uesugi, Takeshi Osada
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Patent number: 9971680Abstract: A semiconductor device including a register controller and a processor which includes a register is provided. The register includes a first circuit and a second circuit which includes a plurality of memory portions. The first circuit and the plurality of memory portions can store data by an arithmetic process of the processor. Which of the plurality of memory portions the data is stored in depends on a routine by which the data is processed. The register controller switches the routine in response to an interrupt signal. The register controller can make any one of the plurality of memory portions which corresponds to the routine store the data in the first circuit every time the routine is switched. The register controller can make data stored in any one of the plurality of memory portions which corresponds to the routine be stored in the first circuit every time the routine is switched.Type: GrantFiled: June 5, 2015Date of Patent: May 15, 2018Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Wataru Uesugi, Tomoaki Atsumi, Naoaki Tsutsui, Hikaru Tamura, Takahiko Ishizu, Takuro Ohmaru
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Publication number: 20170373092Abstract: A retention circuit provided in a logic circuit enables power gating. The retention circuit includes a first terminal, a node, a capacitor, and first to third transistors. The first transistor controls electrical connection between the first terminal and an input terminal of the logic circuit. The second transistor controls electrical connection between an output terminal of the logic circuit and the node. The third transistor controls electrical connection between the node and the input terminal of the logic circuit. A gate of the first transistor is electrically connected to a gate of the second transistor. In a data retention period, the node becomes electrically floating. The voltage of the node is held by the capacitor.Type: ApplicationFiled: July 10, 2017Publication date: December 28, 2017Inventors: Wataru UESUGI, Hikaru TAMURA, Atsuo ISOBE
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Patent number: 9852787Abstract: Provided is a semiconductor device having a memory cell array, which is capable of existing in three power-gating states depending on a non-access period to the memory cell array. The memory cell array includes a plurality of memory cells which each have an SRAM and a nonvolatile memory portion having a transistor with an oxide semiconductor in a channel region. The three power-gating states includes: a first state in which a power-gating to the memory cell array is performed; a second state in which the power-gating is performed on the memory cell array and peripheral circuits which control the memory cell array; and a third state in which, in addition to the memory cell array and the peripheral circuits, a power supply voltage supplying circuit is subjected to the power gating.Type: GrantFiled: March 21, 2017Date of Patent: December 26, 2017Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Takahiko Ishizu, Kiyoshi Kato, Tatsuya Onuki, Wataru Uesugi
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Publication number: 20170337149Abstract: A semiconductor device including a memory which can perform a pipeline operation is provided. The semiconductor device includes a processor core, a bus, and a memory section. The memory section includes a first memory. The first memory includes a plurality of local arrays. The local array includes a sense amplifier array and a local cell array stacked thereover. The local cell array is provided a memory cell including one transistor and one capacitor. The transistor is preferably an oxide semiconductor transistor. The first memory is configured to generate a wait signal. The wait signal is generated when a request for writing data to the same local array is received over two successive clock cycles from the processor core. The wait signal is sent to the processor core via the bus. The processor core stands by for a request for the memory section on the basis of the wait signal.Type: ApplicationFiled: May 9, 2017Publication date: November 23, 2017Inventors: Tatsuya ONUKI, Wataru UESUGI
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Publication number: 20170309325Abstract: A semiconductor device with low power consumption or a semiconductor device with a reduced area is provided. The semiconductor device includes a cell array including a first memory cell and a second memory cell; and a sense amplifier circuit including a first sense amplifier and a second sense amplifier. The cell array is over the sense amplifier circuit. The first sense amplifier is electrically connected to the first memory cell through a first wiring BL. The second sense amplifier is electrically connected to the second memory cell through a second wiring BL. The first sense amplifier and the second sense amplifier are electrically connected to a wiring GBL. The sense amplifier circuit is configured to select one of a potential of the first wiring BL and a potential of the second wiring BL and output the selected potential to the wiring GBL.Type: ApplicationFiled: July 10, 2017Publication date: October 26, 2017Inventors: Tatsuya ONUKI, Kiyoshi KATO, Wataru UESUGI, Takahiko ISHIZU
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Publication number: 20170221899Abstract: An object is to provide a microcontroller (MCU) system with low power consumption. The MCU system includes a CPU, a first memory cell, and a second memory cell. The first memory cell includes a first transistor and a first capacitor. The second memory cell includes a second transistor and a second capacitor. The first memory cell functions as a data memory. The second memory cell functions as a program memory. Each of the first and second transistors contains an oxide semiconductor in a channel formation region. The capacitance of the second capacitor is preferably larger than that of the first capacitor.Type: ApplicationFiled: January 26, 2017Publication date: August 3, 2017Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventors: Wataru UESUGI, Hikaru TAMURA