Abstract: A mobile communication device with multiple subscriptions includes a single baseband-radio frequency (BB-RF) resource chain. A first identity module, such as a subscriber identity module (SIM), a second identity module (e.g., a second SIM), and a controller are communicatively coupled to the single BB-RF resource chain. The first identity module is associated with a first subscription, and the second identity module is associated with a second subscription. The controller may be configured to arbitrate access to the single BB-RF resource chain to perform a first activity that corresponds to the first subscription or a second activity that corresponds to the second subscription. For example, the controller may interrupt a data session processed by the single BB-RF resource chain in response to receiving information indicating that a voice call is to be processed by the single BB-RF resource chain.

Abstract: DSP architectures having improved performance are described. In an exemplary architecture, a DSP includes two MAC units and two ALUs, where one of the ALUs replaces an adder for one of the two MAC units. This DSP may be configured to operate in a dual-MAC/single-ALU configuration, a single-MAC/dual-ALU configuration, or a dual-MAC/dual-ALU configuration. This flexibility allows the DSP to handle various types of signal processing operations and improves utilization of the available hardware. The DSP architectures further includes pipeline registers that break up critical paths and allow operations at a higher clock speed for greater throughput.

Abstract: Demodulator architectures for processing a received signal in a wireless communications system. The demodulator includes a number of correlators coupled to a combiner. Each correlator typically receives and despreads input samples (which are generated from the received signal) with a respective despreading sequence to provide despread samples. Each correlator then decovers the despread samples to provide decovered “half-symbols” and further demodulates the decovered half-symbols with pilot estimates to generate correlated symbols. The decovering is performed with a Walsh symbol having a length (T) that is half the length (2T) of a Walsh symbol used to cover the data symbols in the transmitted signal. The combiner selectively combines correlated symbols from the assigned correlators to provide demodulated symbols. One or more correlators can be assigned to process one or more instances of each transmitted signal.

Abstract: Demodulator architectures for processing a received signal in a wireless communications system. The demodulator includes a number of correlators coupled to a combiner. Each correlator typically receives and despreads input samples (which are generated from the received signal) with a respective despreading sequence to provide despread samples. Each correlator then decovers the despread samples to provide decovered “half-symbols” and further demodulates the decovered half-symbols with pilot estimates to generate correlated symbols. The decovering is performed with a Walsh symbol having a length (T) that is half the length (2T) of a Walsh symbol used to cover the data symbols in the transmitted signal. The combiner selectively combines correlated symbols from the assigned correlators to provide demodulated symbols. One or more correlators can be assigned to process one or more instances of each transmitted signal.

Abstract: A method for overload detection according to one embodiment of the invention includes a control process and a data process. In response to a timing signal, the control process sets a state of a timing indicator. Upon execution of a time-constrained operation, the data process checks the state of the timing indicator. In other embodiments, subsequent to an overload detection, an auxiliary data process is configured to execute in a mode that consumes fewer processing cycles.

Abstract: Demodulator architectures for processing a received signal in a wireless communications system. The demodulator includes a number of correlators coupled to a combiner. Each correlator typically receives and despreads input samples (which are generated from the received signal) with a respective despreading sequence to provide despread samples. Each correlator then decovers the despread samples to provide decovered “half-symbols” and further demodulates the decovered half-symbols with pilot estimates to generate correlated symbols. The decovering is performed with a Walsh symbol having a length (T) that is half the length (2T) of a Walsh symbol used to cover the data symbols in the transmitted signal. The combiner selectively combines correlated symbols from the assigned correlators to provide demodulated symbols. One or more correlators can be assigned to process one or more instances of each transmitted signal.

Abstract: Demodulator architectures for processing a received signal in a wireless communications system. The demodulator includes a number of correlators coupled to a combiner. Each correlator typically receives and despreads input samples (which are generated from the received signal) with a respective despreading sequence to provide despread samples. Each correlator then decovers the despread samples to provide decovered “half-symbols” and further demodulates the decovered half-symbols with pilot estimates to generate correlated symbols. The decovering is performed with a Walsh symbol having a length (T) that is half the length (2T) of a Walsh symbol used to cover the data symbols in the transmitted signal. The combiner selectively combines correlated symbols from the assigned correlators to provide demodulated symbols. One or more correlators can be assigned to process one or more instances of each transmitted signal.

Abstract: Demodulator architectures for processing a received signal in a wireless communications system. The demodulator includes a number of correlators coupled to a combiner. Each correlator typically receives and despreads input samples (which are generated from the received signal) with a respective despreading sequence to provide despread samples. Each correlator then decovers the despread samples to provide decovered “half-symbols” and further demodulates the decovered half-symbols with pilot estimates to generate correlated symbols. The decovering is performed with a Walsh symbol having a length (T) that is half the length (2T) of a Walsh symbol used to cover the data symbols in the transmitted signal. The combiner selectively combines correlated symbols from the assigned correlators to provide demodulated symbols. One or more correlators can be assigned to process one or more instances of each transmitted signal.

Abstract: An apparatus and method for echo cancellation is presented. The echo canceller comprises an adaptive filter that tracks the impulse response of the echo path and produces an estimate of the echo. Filter adaptation is controlled by a controller based on the rate of the far-end speech signal, the rate of the near-end signal, an acoustic loss measure, and a double talk hangover indicator. The controller may also comprise a step size adaptation unit for determining the adaptation step size of the adaptive filter. In addition, the controller may comprise a noise replacement unit, which controls replacement of the echo residual signal with comfort noise to ensure echo is completely rejected when only the far-end speaker is talking.

Abstract: DSP architectures having improved performance are described. In an exemplary architecture, a DSP includes two MAC units and two ALUs, where one of the ALUs replaces an adder for one of the two MAC units. This DSP may be configured to operate in a dual-MAC/single-ALU configuration, a single-MAC/dual-ALU configuration, or a dual-MAC/dual-ALU configuration. This flexibility allows the DSP to handle various types of signal processing operations and improves utilization of the available hardware. The DSP architectures further includes pipeline registers that break up critical paths and allow operations at a higher clock speed for greater throughput.

Abstract: Demodulator architectures for processing a received signal in a wireless communications system. The demodulator includes a number of correlators coupled to a combiner. Each correlator typically receives and despreads input samples (which are generated from the received signal) with a respective despreading sequence to provide despread samples. Each correlator then decovers the despread samples to provide decovered “half-symbols” and further demodulates the decovered half-symbols with pilot estimates to generate correlated symbols. The decovering is performed with a Walsh symbol having a length (T) that is half the length (2T) of a Walsh symbol used to cover the data symbols in the transmitted signal. The combiner selectively combines correlated symbols from the assigned correlators to provide demodulated symbols. One or more correlators can be assigned to process one or more instances of each transmitted signal.

Abstract: A spread spectrum wireless device (100) may include a receiver (110), a searcher (128), a search controller (130) and other features. The search controller (130) selectively generates control signals to control the searcher (128), which searches for a spread-spectrum signal. In one embodiment, the architecture of the searcher (128) is dynamically configurable by the search controller (130) to selectively search multiple channels using multiple frequency bins for the signal.

Abstract: A spread spectrum wireless device (100) may include a receiver (110), a searcher (128), a search controller (130) and other features. The search controller (130) selectively generates control signals to control the searcher (128), which searches for a spread-spectrum signal. In one embodiment, the architecture of the searcher (128) is dynamically configurable by the search controller (130) to selectively search multiple channels using multiple frequency bins for the signal.

Abstract: Demodulator architectures for processing a received signal in a wireless communications system. The demodulator includes a number of correlators coupled to a combiner. Each correlator typically receives and despreads input samples (which are generated from the received signal) with a respective despreading sequence to provide despread samples. Each correlator then decovers the despread samples to provide decovered “half-symbols” and further demodulates the decovered half-symbols with pilot estimates to generate correlated symbols. The decovering is performed with a Walsh symbol having a length (T) that is half the length (2T) of a Walsh symbol used to cover the data symbols in the transmitted signal. The combiner selectively combines correlated symbols from the assigned correlators to provide demodulated symbols. One or more correlators can be assigned to process one or more instances of each transmitted signal.

Abstract: An apparatus and method for echo cancellation is presented. The echo canceller comprises an adaptive filter that tracks the impulse response of the echo path and produces an estimate of the echo. Filter adaptation is controlled by a controller based on the rate of the far-end speech signal, the rate of the near-end signal, an acoustic loss measure, and a double talk hangover indicator. The controller may also comprise a step size adaptation unit for determining the adaptation step size of the adaptive filter. In addition, the controller may comprise a noise replacement unit, which controls replacement of the echo residual signal with comfort noise to ensure echo is completely rejected when only the far-end speaker is talking.

Abstract: A method for overload detection according to one embodiment of the invention includes a control process and a data process. In response to a timing signal, the control process sets a state of a timing indicator. Upon execution of a time-constrained operation, the data process checks the state of the timing indicator. In other embodiments, subsequent to an overload detection, an auxiliary data process is configured to execute in a mode that consumes fewer processing cycles.

Abstract: A digital signal processor (DSP) employs a variable-length instruction set. A portion of the variable-length instructions may be stored in adjacent locations within memory space with the beginning and ending of instructions occurring across memory word boundaries. The instructions may contain variable numbers of instruction fragments. Each instruction fragment causes a particular operation, or operations, to be performed allowing multiple operations during each clock cycle. The DSP includes multiple data buses, and in particular three data buses. The DSP may also use a register bank that has registers accessible by at least two processing units, allowing multiple operations to be performed on a particular set of data by the multiple processing units, without reading and writing the data to and from a memory. an instruction fetch unit that receives instructions of variable length stored in an instruction memory. An instruction memory may advantageously be separate from the three data memories.

Abstract: The invention is a digital signal processor architecture that is designed to speed up frequently-used signal processing computations, such as FIR filters, correlations, FFTs, and DFTs. The architecture uses a coupled dual-MAC architecture (MAC1), (MAC2) and attaches a dual-MAC coprocessor (MAC3), (MAC4) onto it in a unique way to achieve a significant increase in processing capability.

Abstract: A spread spectrum wireless device (100) may include a receiver (110), a searcher (128), a search controller (130) and other features. The search controller (130) selectively generates control signals to control the searcher (128), which searches for a spread-spectrum signal. In one embodiment, the architecture of the searcher (128) is dynamically configurable by the search controller (130) to selectively search multiple channels using multiple frequency bins for the signal.

Abstract: An apparatus and method for echo cancellation is presented. The echo canceller comprises an adaptive filter that tracks the impulse response of the echo path and produces an estimate of the echo. Filter adaptation is controlled by a controller based on the rate of the far-end speech signal, the rate of the near-end signal, an acoustic loss measure, and a double talk hangover indicator. The controller may also comprise a step size adaptation unit for determining the adaptation step size of the adaptive filter. In addition, the controller may comprise a noise replacement unit, which controls replacement of the echo residual signal with comfort noise to ensure echo is completely rejected when only the far-end speaker is talking.