Abstract: A method and apparatus are described for providing error correcting code (ECC) which may be incorporated into a computer system which includes one of a plurality of memory configurations and which may include a pre-existing error control feature. A data store operation causes the receipt of a word including data bits and check bits generated by a pre-existing error control feature. The data and check bits of the received word are used to generate additional check bits based upon the configuration of the computer system memory. The additionally generated check bits are stored in the memory along with the received word. Upon a subsequent data fetch operation which retrieves the word and check bits the check bits are decoded thereby providing error detection and correction in the retrieved word for single and multiple bit errors including the failure of an entire memory chip.

Abstract: A method and apparatus are described for providing error correcting code (ECC) which may be incorporated into a computer system which includes one of a plurality of memory configurations and which may include a pre-existing error control feature. A data store operation causes the receipt of a word including data bits and check bits generated by a pre-existing error control feature. The data and check bits of the received word are used to generate additional check bits based upon the configuration of the computer system memory. The additionally generated check bits are stored in the memory along with the received word. Upon a subsequent data fetch operation which retrieves the word and check bits the check bits are decoded thereby providing error detection and correction in the retrieved word for single and multiple bit errors including the failure of an entire memory chip.

Abstract: A method and apparatus are described for providing error correcting code (ECC) which may be incorporated into a computer system which includes one of a plurality of memory configurations and which may include a pre-existing error control feature. A data store operation causes the receipt of a word including data bits and check bits generated by a pre-existing error control feature. The data and check bits of the received word are used to generate additional check bits based upon the configuration of the computer system memory. The additionally generated check bits are stored in the memory along with the received word. Upon a subsequent data fetch operation which retrieves the word and check bits the check bits are decoded thereby providing error detection and correction in the retrieved word for single and multiple bit errors including the failure of an entire memory chip.