Patents by Inventor Wayne D. Tran

Wayne D. Tran has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10268542
    Abstract: An apparatus comprises a controller to retrieve data from a non-volatile memory, and an error correction module operable on the controller to read a memory cell of the non-volatile memory at a first set of sense conditions comprising a multiplicity of sense conditions. The error correction module may be further operable to set a first set of bits in an encoded output, the first set of bits comprising a logical state bit to indicate a logical state of the memory cell and one or more additional bits in the encoded output to indicate accuracy of the logical state bit based upon results of the read at the first set of sense conditions, the first set of sense conditions comprising a greater number than that of the first set of bits.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: April 23, 2019
    Assignee: INTEL CORPORATION
    Inventors: Matthew Goldman, Wayne D. Tran, Aliasgar S. Madraswala, Sungho Park
  • Patent number: 10268578
    Abstract: In one embodiment, a nonvolatile memory of a component such as a storage drive preserves write data in the event of a write data programming failure in the memory. Write data is preserved in the event of cached writes by data preservation logic in registers and data recovery logic recovers the preserved data and outputs the recovered data from the storage drive. Other aspects are described herein.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: April 23, 2019
    Assignee: INTEL CORPORATION
    Inventors: Shankar Natarajan, Aliasgar S. Madraswala, Wayne D. Tran
  • Publication number: 20190102296
    Abstract: In one embodiment, a nonvolatile memory of a component such as a storage drive preserves write data in the event of a write data programming failure in the memory. Write data is preserved in the event of cached writes by data preservation logic in registers and data recovery logic recovers the preserved data and outputs the recovered data from the storage drive. Other aspects are described herein.
    Type: Application
    Filed: September 29, 2017
    Publication date: April 4, 2019
    Inventors: Shankar NATARAJAN, Aliasgar S. MADRASWALA, Wayne D. TRAN
  • Publication number: 20170315866
    Abstract: An apparatus may comprise a controller to retrieve data from a non-volatile memory, and an error correction module operable on the controller to read a memory cell of the non-volatile memory at a first set of sense conditions comprising a multiplicity of sense conditions. The error correction module may be further operable to set a first set of bits in an encoded output, the first set of bits comprising a logical state bit to indicate a logical state of the memory cell and one or more additional bits in the encoded output to indicate accuracy of the logical state bit based upon results of the read at the first set of sense conditions, the first set of sense conditions comprising a greater number than that of the first set of bits. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: February 27, 2017
    Publication date: November 2, 2017
    Applicant: INTEL CORPORATION
    Inventors: MATTHEW GOLDMAN, WAYNE D. TRAN, ALIASGAR S. MADRASWALA, SUNGHO PARK
  • Patent number: 9582357
    Abstract: Various embodiments are generally directed to an apparatus, method and other techniques to retrieve data from a non-volatile memory, and to read a memory cell of the non-volatile memory at a first set of sense conditions comprising a multiplicity of sense conditions. Embodiments also include an apparatus, method and other techniques to set a first set of bits in an encoded output, the first set of bits comprising a logical state bit to indicate a logical state of the memory cell and one or more additional bits in the encoded output to indicate accuracy of the logical state bit based upon results of the read at the first set of sense conditions, the first set of sense conditions comprising a greater number than that of the first set of bits.
    Type: Grant
    Filed: March 29, 2012
    Date of Patent: February 28, 2017
    Assignee: INTEL CORPORATION
    Inventors: Matthew Goldman, Wayne D. Tran, Aliasgar S. Madraswala, Sungho Park
  • Publication number: 20140089764
    Abstract: An apparatus may comprise a controller to retrieve data from a non-volatile memory, and an error correction module operable on the controller to read a memory cell of the non-volatile memory at a first set of sense conditions comprising a multiplicity of sense conditions. The error correction module may be further operable to set a first set of bits in an encoded output, the first set of bits comprising a logical state bit to indicate a logical state of the memory cell and one or more additional bits in the encoded output to indicate accuracy of the logical state bit based upon results of the read at the first set of sense conditions, the first set of sense conditions comprising a greater number than that of the first set of bits. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: March 29, 2012
    Publication date: March 27, 2014
    Inventors: Matthew Goldman, Wayne D. Tran, Aliasgar S. Madraswala, Sungho Park
  • Patent number: 6038294
    Abstract: A modem device is described. The modem device comprises a first connector allowing coupling to a telecommunications transmission system, a second connector allowing coupling to a computer system, and a selector capable of receiving a mode select signal and capable of automatically selecting between operational modes in response to the mode select signal. It also comprises a circuit capable of receiving signals from the telecommunications transmission system in a selected operational mode and transmitting signals to a computer system. The circuit also is capable of receiving signals from the computer system and transmitting signals to the telecommunications transmission system in the selected operational mode.
    Type: Grant
    Filed: December 27, 1996
    Date of Patent: March 14, 2000
    Assignee: Intel Corporation
    Inventors: Wayne D. Tran, Michael E. Pierce