Abstract: A first transparent latch receives a first synchronised signal changing its logic state synchronously with respect to a clock signal. A second transparent latch receives a second synchronised signal output by the first latch. When the clock signal has a first logic state the first latch has a non-responsive state and the second latch has a responsive state, and when the clock signal has a second logic state the first latch has the responsive state and the second latch has the non-responsive state. The change in logic state of a third synchronised signal output by the second latch is guaranteed to occur in a particular half-cycle of the clock signal, irrespective of process/voltage/temperature (PVT) variations of the circuitry.

Abstract: A first transparent latch (22) receives a first synchronised signal (S1) which changes its logic state synchronously with respect to a clock signal (CLK). A second transparent latch (24) receives a second synchronised signal (S2) output by the first latch (22). When the clock signal has a first logic state (H) the first latch (22) has a non-responsive state and the second latch has a responsive state, and when the clock signal has a second logic state (L) the first latch has the responsive state and the second latch has the non-responsive state.