Abstract: A system is presented for a plurality of computer nodes in mutual data communication to execute logic in a coordinated manner. The approach features aligning the definition of the time in the nodes so that each node has essentially the same definition of time; defining a schedule of communications for each computer node, with the schedule having future moments defined for initiating each communication; communicating each schedule to its respective node; and initiating each communication at the time defined in the schedule. The computer network has a message carrier supporting multiple communication paths; a plurality of computers coupled to the message carrier, a clock system for maintaining time synchronism among the computers; and a scheduler coupled to the message carrier for determining the sequence of communication between the computers. The message carrier establishes communication between selected computers based on the time-deterministic tasks being performed by the computers.

Abstract: A system is presented for a plurality of computer nodes in mutual data communication to execute logic in a coordinated manner. The approach features aligning the definition of the time in the nodes so that each node has essentially the same definition of time; defining a schedule of communications for each computer node, with the schedule having future moments defined for initiating each communication; communicating each schedule to its respective node; and initiating each communication at the time defined in the schedule. The computer network has a message carrier supporting multiple communication paths; a plurality of computers coupled to the message carrier, a clock system for maintaining time synchronism among the computers; and a scheduler coupled to the message carrier for determining the sequence of communication between the computers. The message carrier establishes communication between selected computers based on the time-deterministic tasks being performed by the computers.

Abstract: A dedicated context cycling microprocessor which features a plurality of input/output circuits for receiving and transmitting information and an individual set of dedicated on-board resources for each plurality of processing contexts. A distinct processing context is provided for each of a plurality of the input/output circuits, and a timed context is also provided for concurrently scheduling multiple processing contexts and enforcing time constraints associated with this schedule. The timed context has a pseudo-queue list which represents an ordered set of data parameters and program memory addresses for scheduling each of the processing contexts. The dedicated on-board resources include a plurality of registers for each of the processing contexts, such as at least one general purpose register and a program counter. A multiplexer circuit is also provided for moving data between the input/output circuits, the dedicated registers of the processing contexts and the computational unit.

Abstract: A massively multiplexed central processing unit ("CPU") which has a plurality of independent computational circuits, a separate internal result bus for transmitting the resultant output from each of these computational circuits, and a plurality of general purpose registers coupled to each of the computational circuits. Each of the general purpose registers have multiplexed input ports which are connected to each of the result buses. Each of the general purpose registers also have an output port which is connected to a multiplexed input port of at least one of the computational circuits. Each of the computational circuits are dedicated to at least one unique mathematical function, and at least one of the computational circuits include at least one logical function. At least one of the computational circuits includes a plurality of concurrently operable mathematical and logical processing circuits, and an output multiplexer for selecting one of the resultant outputs for transmission on its result bus.

Abstract: A method of input signal resolution in a process control system where each of the actively redundant process control computers performs a common arbitration process on corresponding input signals. Blocks of corresponding input signals are mutually exchanged by the actively redundant process control computers, and an initial check is made to determine if these input signals are valid. For input signals representing valid analog values, a determination is made as to whether a predefined tolerance has been exceeded between corresponding input signals in the present process control cycle. When the predefined tolerance has been exceeded, then a check will be made to determine the predefined tolerance was also exceeded in the last process control cycle. If the predefined tolerance was not exceeded in the last process control cycle, then the analog input value selected during the last process control cycle will be employed in the present process control cycle.

Abstract: An extended Harvard architecture memory system which features an address store for containing an ordered sequence of program memory addresses, and a value store for containing a series of related data value sets. Each of the addresses contained in the address store is associated with a distinct set of instructions, such as a subroutine, that is contained in the program memory. The address store may also contain the address of one or more instruction arguments that are, in turn, contained in the value store or in a separate data memory. Both the address store and the value store are preferably connected to the same data communication path which is used by the data memory of the computer. The value store also includes a logic interface for enabling a plurality of different address increments to be programmably selected.

Abstract: A method and an apparatus are taught in which variable analog data, representative of a plurality of physical parameters are recorded on a thermo-sensitive recording paper which is movable along an axis representative of time. A thermal recording head is transversely movable over the recording paper for sequentially recording the variable analog data in their order of value in a unidirectional sweep of the recording head over the paper. The variable analog data signals arriving in the recorder are updated to obtain their instantaneous values and are gathered and transferred to memory locations in a sequential order. The sequential analog data is then tabulated in the order of value in an ascending or declining magnitude and recorded in such order on the recording paper. Successive recordings of tabulated analog values provide tracings on the recording paper giving, in graphic form, a continuous read-out of physical parameters.