Abstract: A microword generation mechanism is provided for producing the sequences of microwords used to control the execution of processor instructions in a microprogrammed digital data processor. This microword generation mechanism includes programmable logic array means responsive to the processor instructions for producing the appropriate microword sequences. The microword generation mechanism also includes condition indicator circuitry for supplying indicator signals indicating whether the results of arithmetic and logic operations in the processor meet certain types of conditions. The microword generation mechanism further includes a condition testing programmable logic array responsive to the condition field of a conditional branch type processor instruction for testing the appropriate indicator signal or signals and causing a branch type microword sequence to be produced if the specified condition is met.

Abstract: A microword generation mechanism is provided for producing the sequences of microwords used to control the execution of processor instructions in a microprogrammed digital data processor. This microword generation mechanism includes a first programmable logic array mechanism responsive to the processor instruction to be executed for providing the first microword needed in the execution of such instruction. This microword generation mechanism also includes a second programmable logic array mechanism responsive to the processor instruction to be executed for providing the second microword needed in the execution of such instruction. This microword generation mechanism further includes at least one additional programmable logic array mechanism responsive to the processor instruction to be executed for providing the remainder of the microwords needed to execute such instruction.

Abstract: A microword generation mechanism is provided for producing the sequences of microwords used to control the execution of processor instructions in a microprogrammed digital data processor. This microword generation mechanism includes a first programmable logic array mechanism responsive to the processor instruction to be executed for providing the first microword needed in the execution of such instruction. This microword generation mechanism also includes a second programmable logic array mechanism responsive to the processor instruction to be executed for providing the second microword needed in the execution of such instruction. This microword generation mechanism further includes at least one additional programmable logic array mechanism responsive to the processor instruction to be executed for providing the remainder of the microwords needed to execute such instruction.

Abstract: Apparatus and method for decoding computer operation codes. The operation code is decoded into a single product term in the AND array of a programmable logic array. That single product term is then processed through a clock driven sequencer to generate a plurality of sequential product terms. These sequential product terms are decoded by the OR array of the programmable logic array to generate a plurality of sequential time states comprising the decoded operation code.

Abstract: A microword control system is provided for producing the sequences of microwords used to control the execution of processor instructions in a microprogrammed digital data processor. This microword control system includes a plurality of programmable logic array mechanisms responsive to the processor instruction to be executed for individually producing different ones of the microwords needed to execute such instruction. This microword control system also includes microword-responsive control circuitry for controlling the operation of the data processor. This microword control system further includes multiplexing circuitry for supplying microwords from different ones of the programmable logic array mechanisms to the control circuitry during different time intervals.

Abstract: An integrated circuit mechanism is provided for coupling the separate sets of output lines from a plurality of programmable logic arrays to the same set of bus lines of plural-line signal transfer bus. This coupling mechanism includes precharge circuitry for precharging each of the bus lines during a first time interval. This coupling mechanism also includes a separate strobe signal line for each programmable logic array and circuitry for activating one of the strobe signal lines during a second time interval for selecting a particular programmable logic array. This coupling mechanism further includes a separate output buffer for each programmable logic array. Each such output buffer includes a plurality of buffer stages for individually coupling the different ones of the programmable logic array output lines to their respective bus lines.

Abstract: A digital data signal transfer mechanism is provided for use in large scale integration digital data processor circuitry formed on an integrated circuit chip. The signal transfer mechanism includes a plural-bit data bus formed on the integrated circuit chip for transferring plural-bit binary data signals between different locations on the chip. The signal transfer mechanism also includes plural-bit signal source circuitry and plural-bit signal destination circuitry formed on the integrated circuit chip and coupled to the plural-bit data bus for respectively supplying plural-bit data signals to and receiving plural-bit data signals from the bus.

Abstract: Self-test techniques for checking driver circuits connected to a bus are described that particularly involve the detection and isolation of failures in off-chip-drivers and connections.

Abstract: A tristate driver circuit is provided on an integrated circuit chip for driving a bus line or signal line located off of the chip. This circuit very rapidly charges the bus line or signal line to positive voltage level each time and just before it switches to its tristate or high impedance output condition. This eliminates the need for a pull-up resistor or pull-up transistor to be connected to the off-chip bus line or signal line.

Abstract: As a specific improvement to a previously known PLA (Programmed Logic Array) structure, formed by FET devices in serially chained charge transfer circuits, the presently disclosed "modified" PLA structure comprises a combination of: (a) level shifting circuitry, integrated into bit partitioning stages of the known structure, for reducing voltage swings in the outputs of those stages and thereby reducing spurious couplings to the following AND array stage as well as decreasing operational delays of the latter stage; (b) discrete capacitance, added at the output end of the OR array stage of the known structure, for sustaining and reinforcing charge conditions accumulated in that stage prior to readout (validation clocking) of that stage; and (c) a source of time related clocking functions coupled to stages of the modified structure, with the timing relationships selected so as to reduce operational delays of the entire structure while improving its integrity of operation.

Abstract: Improved tristate control circuitry is provided for a driver circuit formed on an integrated circuit chip. A parallel-connected combination of a depletion mode transistor and an enhancement mode transistor is connected in series in the voltage supply path for the driver circuit for controlling whether the driver circuit is in an active mode or a standby mode by controlling the supplying of operating voltage thereto. A further enhancement mode transistor provides a shunting action between the driver circuit side of the parallel-connected transistors and circuit ground to further aid in the control of the driver circuit operating mode.

Abstract: A plurality of programmable logic arrays (PLA's) operate in parallel, each to decode an operation code (OP code). A portion of the OP code is decoded to select one of the PLA's, and the decoded OP code from the selected PLA is gated through a multiplexer to provide the control code corresponding to the OP code.

Abstract: A logic performing cell for use in array structures is provided which allows greater density fabrication in integrated circuits and reduces operational delays. The array has a plurality of output lines intercepted by a plurality of orthogonally oriented input lines, with elements in the form of a three terminal device located at each of the intersections of the input and output lines so that logical functions are performed on interrogation signals placed on the input lines and the responses thereto placed on the output lines. The three terminal device transfer gates are connected in groups of series strings which are connected in parallel to a recombination line. These groups of series connected transfer gates comprise a programmed mix of enhancement and depletion devices. Each logic function of each group of transfer gates establishes an output which, when coupled to the recombining output circuit line, provides an overall logic function for the logic performing cell.

Abstract: A processor is provided that is fabricated on a single semiconductor substrate. The processor includes an AND array for receiving program instructions from input sources external of the processor and for generating product signals. An OR array is provided and interconnected to the AND array for receiving the product signals and for generating a plurality of control signals. A register array receives ones of the plurality of control signals and transfers data between the processor and data sources external of the processor. An arithmetic and logic unit array is also provided on the semiconductor substrate and interconnected to the register array and the OR array for executing operations on data received from the register array in accordance with ones of the plurality of control signals to generate output data.