Abstract: A network includes a service selection gateway that receives information from a network user having a network locator address in order to establish a communications session and an identity of the network user. A client service gateway can receive a request from the network user upon establishment of the communications session. In response to the request, the client service gateway determines if there is an association in a local memory for the network locator address and an identity of the network user, obtains additional information associated with the network user, and processes the request according to the additional information. If an association is not stored in the local memory, the client service gateway sends a query for the identity of the network user to the service selection gateway.

Abstract: Method for managing connections on a connection-oriented network such as an ATM network, for use with devices communicating according to a connectionless communication protocol such as IP over Ethernet. Roughly described, a bridging network element (BNE) resides at the ATM point-of-presence through which a data network accesses the ATM network. When the BNE receives an internet ARP (IARP) request from the data network for forwarding onto the ATM network, it forwards it instead to an IARP server. In addition to responding to the IARP request, the IARP server also regards the IARP request as a trigger, and in response thereto, causes the ATM network to establish a connection between the BNE point-of-presence and another point-of-presence on the ATM network through which the target address can be reached.

Abstract: A network communications adapter interconnects a plurality of digital computing resources for mutual data exchange in which a high performance, large capacity common memory is provided with a pair of external buses which allows multiple processors to store information in and read information from the common memory. The common memory is configured into two banks, each bank operating independently and concurrently under control of bus switching logic with separate address, control and data buses. The common memory typically provides 400 megabits per second of bandwidth to the multiple attached thirty-two and sixteen bit processors which may be coupled either to both buses simultaneously or individually to the two buses. The bus switching logic then allocates all of the available bandwidth to the individual processors coupled to the buses based upon a predetermined profile established at the time of system installation. Also included in the bus switch logic is circuitry for broadcasting a processor I.D.