Patents by Inventor Wayne Tran

Wayne Tran has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10658056
    Abstract: An embodiment of a semiconductor package apparatus may include technology to attempt to program data in a first portion of a nonvolatile memory, determine if the attempt was successful, and recover the data to a second portion of the nonvolatile memory with an internal data move operation if the attempt is determined to be not successful. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: May 19, 2020
    Assignee: Intel Corporation
    Inventors: Shankar Natarajan, Wayne Tran
  • Publication number: 20190180830
    Abstract: An embodiment of a semiconductor package apparatus may include technology to attempt to program data in a first portion of a nonvolatile memory, determine if the attempt was successful, and recover the data to a second portion of the nonvolatile memory with an internal data move operation if the attempt is determined to be not successful. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: December 22, 2017
    Publication date: June 13, 2019
    Inventors: Shankar Natarajan, Wayne Tran
  • Publication number: 20190041947
    Abstract: Technologies for dynamically managing a power state of a first endpoint device and a second endpoint device that are operatively coupled to a data bus of a compute device include communication monitor circuitry and power state manager circuitry. The communication monitor circuitry is configured to detect an activation signal on the data bus. The power state manager circuitry is configured to activate, in response to detection of the activation signal, the first and second endpoint devices that are operatively coupled to the data bus into a high power state from a low power state, determine, in response to activation of the first and second endpoint devices, which activated endpoint device is requested to perform work associated with the activation signal, and operate, in response to determination that the second endpoint device has no pending work to perform, the second endpoint device to return to the low power state.
    Type: Application
    Filed: June 28, 2018
    Publication date: February 7, 2019
    Inventors: Shankar Natarajan, Wayne Tran, Vishal Mannapur, Anthony Giardina
  • Patent number: 7225318
    Abstract: In a continuous burst memory read operation, a dynamic prefetch circuit compares a prefetched address with a received address. If the compared addresses are identical, the prefetched address is applied to the memory; else the prefetched address is preempted by the received address, the received address is coupled to the memory, and output data corresponding to the prefetched address is interrupted.
    Type: Grant
    Filed: October 8, 2003
    Date of Patent: May 29, 2007
    Assignee: Intel Corporation
    Inventors: Wayne Tran, Henry Wong
  • Publication number: 20050081014
    Abstract: In a continuous burst memory read operation, a dynamic prefetch circuit compares a prefetched address with a received address. If the compared addresses are identical, the prefetched address is applied to the memory; else the prefetched address is preempted by the received address, the received address is coupled to the memory, and output data corresponding to the prefetched address is interrupted.
    Type: Application
    Filed: October 8, 2003
    Publication date: April 14, 2005
    Inventors: Wayne Tran, Henry Wong