Patents by Inventor Webster B. Meier

Webster B. Meier has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Staggered refresh for dram array
    Patent number: 4887240
    Abstract: According to the present invention, each successive refresh to the multiple banks of a DRAM array is staggered by one clock period. Thus, the time required to refresh one row in each DRAM of each bank at 10 MHz, for example, is equal to 0.7 .mu.sec., or 4.4% of the total allowable maximum time between refresh cycles. This staggered refresh technique avoids large power supply current spikes while minimizing the effect on memory access bandwidth.
    Type: Grant
    Filed: December 15, 1987
    Date of Patent: December 12, 1989
    Assignee: National Semiconductor Corporation
    Inventors: Timothy L. Garverick, Farid A. Yazdy, Richard D. Henderson, Webster B. Meier