Abstract: An example method includes encoding, in a video bitstream, a first syntax element specifying whether affine model based motion compensation is enabled; based on affine model based motion compensation being enabled, encoding, in the video bitstream, a second syntax element specifying a maximum number of subblock-based merging motion vector prediction candidates, wherein a value of the second syntax element is constrained based on a value other than a value of the first syntax element; and encoding a picture of the video data based on the maximum number of subblock-based merging motion vector prediction candidates.

Abstract: A light-emitting diode chip is described. The light-emitting diode chip includes a light-emitting structure, a first electrode, and a second electrode. The first electrode is disposed on the light-emitting structure and is electrically connected to the light-emitting structure. The second electrode is disposed on the light-emitting structure, and the second electrode and the first electrode are located on the same side of the light-emitting structure, wherein the second electrode is electrically connected to the light-emitting structure. The light-emitting diode chip has a first surface and a second surface which are opposite to each other, and a side surface connected between the first surface and the second surface. The side surface is substantially perpendicular to the first surface and the second surface, and an included angle between the side surface and the first surface is between 86 degrees and 94 degrees.

Abstract: A micro light-emitting film structure includes a first conductivity type semiconductor film, a light-emitting film, a second conductivity type semiconductor film, a first contact electrode, and a second contact electrode. The first conductivity type semiconductor film has first and second surfaces opposite to each other. The second surface includes an asperity. A height difference of relief of the asperity is less than or equal to 1 ?m. The light-emitting film is disposed on the first surface. The second conductivity type semiconductor film is connected to the light-emitting film sandwiched between the second conductivity type semiconductor film and the first conductivity type semiconductor film. The first contact electrode is connected to the first conductivity type semiconductor film. The second contact electrode is connected to the second conductivity type semiconductor film. A thickness of the micro light-emitting film structure is equal to or smaller than 10 ?m.

Abstract: A micro light-emitting diode includes an epitaxial structure, an insulation layer, a first electrode, and a second electrode. The epitaxial structure includes a first semiconductor layer, a light-emitting layer, and a second semiconductor layer. The epitaxial structure has a cavity penetrating the second semiconductor layer and the light-emitting layer and exposing a portion of the first semiconductor layer. The insulation layer covers the epitaxial structure, and a side surface and a bottom surface of the cavity. The insulation layer has a first hole exposing a portion of the second semiconductor layer, and a second hole exposing a portion of the bottom surface. The first electrode covers the exposed portion of the bottom surface. The second electrode covers the exposed portion of the second semiconductor layer and is distant from the first electrode. The cavity is distant from an edge of the micro LED.

Abstract: Implementations of the disclosure provide a method of fabricating an integrated circuit (IC). The method includes receiving an IC design layout; performing optical proximity correction (OPC) process to the IC design layout to produce a corrected IC design layout; and verifying the corrected IC design layout using a machine learning algorithm. The post OPC verification includes using the machine learning algorithm to identify one or more features of the corrected IC design layout; comparing the one or more identified features to a database comprising a plurality of features; and verifying the corrected IC design layout based on labels in the database associated with the plurality of features.

Abstract: Optical proximity correction (OPC) based computational lithography techniques are disclosed herein for enhancing lithography printability. An exemplary mask optimization method includes receiving an integrated circuit (IC) design layout having an IC pattern; generating target points for a contour corresponding with the IC pattern based on a target placement model, wherein the target placement model is selected based on a classification of the IC pattern; and performing an OPC on the IC pattern using the target points, thereby generating a modified IC design layout. The method can further include fabricating a mask based on the modified IC design layout. The OPC can select an OPC model based on the classification of the IC pattern. The OPC model can weight the target placement model.

Abstract: A method of manufacturing an integrated circuit includes generating a first layout design based on design criteria, performing a color mapping between the first layout design and a standard cell layout design thereby generating a via color layout design, and manufacturing the integrated circuit based on the via color layout design. The first layout design has a first set of vias divided into sub-sets of vias based on a corresponding color indicating that vias of the sub-set of vias with a same color, and vias of the sub-set of vias with a different color. The standard cell layout design has a second set of vias arranged in standard cells. The via color layout design has a third set of vias including a portion of the second set of vias and corresponding locations, and color of the corresponding sub-set of vias.

Abstract: Implementations of the disclosure provide a method of fabricating an integrated circuit (IC). The method includes receiving an IC design layout; performing optical proximity correction (OPC) process to the IC design layout to produce a corrected IC design layout; and verifying the corrected IC design layout using a machine learning algorithm. The post OPC verification includes using the machine learning algorithm to identify one or more features of the corrected IC design layout; comparing the one or more identified features to a database comprising a plurality of features; and verifying the corrected IC design layout based on labels in the database associated with the plurality of features.

Abstract: The invention provides an LED including a first-type semiconductor layer, an emitting layer, a second-type semiconductor layer, a first electrode, a second electrode, a Bragg reflector structure, a conductive layer and insulation patterns. The first electrode and the second electrode are located on the same side of the Bragg reflector structure. The conductive layer is disposed between the Bragg reflector structure and the second-type semiconductor layer. The insulation patterns are disposed between the conductive layer and the second-type semiconductor layer. Each insulating layer has a first surface facing toward the second-type semiconductor layer, a second surface facing away from the second-type semiconductor layer, and an inclined surface. The inclined surface connects the first surface and the second surface and is inclined with respect to the first surface and the second surface.

Abstract: A novel miniaturized horizontal split-wave orthomode transducer includes a common channel portion, a first polarized channel portion and a second polarized channel portion, and the centers of the openings of the first polarized channel and the second polarized channel are coaxially and respectively arranged on two opposite sides of the common channel portion to save the bend and extended structure at the rear end of the horizontal split-wave orthomode transducer and also save the occupied space since there is no need to guide signals in one of the polarization directions to the rear and return the signals, so as to further achieve the effects of improving the flexibility of installing the transducer, providing a good isolation between electromagnetic signals in different polarization directions and preventing the interference occurred between the electromagnetic signals.

Abstract: Implementations of the disclosure provide a method of fabricating an integrated circuit (IC). The method includes receiving an IC design layout; performing optical proximity correction (OPC) process to the IC design layout to produce a corrected IC design layout; and verifying the corrected IC design layout using a machine learning algorithm. The post OPC verification includes using the machine learning algorithm to identify one or more features of the corrected IC design layout; comparing the one or more identified features to a database comprising a plurality of features; and verifying the corrected IC design layout based on labels in the database associated with the plurality of features.

Abstract: A method of manufacturing an integrated circuit includes generating a first layout design based on design criteria, performing a color mapping between the first layout design and a standard cell layout design thereby generating a via color layout design, and manufacturing the integrated circuit based on the via color layout design. The first layout design has a first set of vias divided into sub-sets of vias based on a corresponding color indicating that vias of the sub-set of vias with a same color, and vias of the sub-set of vias with a different color. The standard cell layout design has a second set of vias arranged in standard cells. The via color layout design has a third set of vias including a portion of the second set of vias and corresponding locations, and color of the corresponding sub-set of vias.

Abstract: Optical proximity correction (OPC) based computational lithography techniques are disclosed herein for enhancing lithography printability. An exemplary mask optimization method includes receiving an integrated circuit (IC) design layout having an IC pattern; generating target points for a contour corresponding with the IC pattern based on a target placement model, wherein the target placement model is selected based on a classification of the IC pattern; and performing an OPC on the IC pattern using the target points, thereby generating a modified IC design layout. The method can further include fabricating a mask based on the modified IC design layout. The OPC can select an OPC model based on the classification of the IC pattern. The OPC model can weight the target placement model.

Abstract: A novel miniaturized horizontal split-wave orthomode transducer includes a common channel portion, a first polarized channel portion and a second polarized channel portion, and the centers of the openings of the first polarized channel and the second polarized channel are coaxially and respectively arranged on two opposite sides of the common channel portion to save the bend and extended structure at the rear end of the horizontal split-wave orthomode transducer and also save the occupied space since there is no need to guide signals in one of the polarization directions to the rear and return the signals, so as to further achieve the effects of improving the flexibility of installing the transducer, providing a good isolation between electromagnetic signals in different polarization directions and preventing the interference occurred between the electromagnetic signals.

Abstract: A method of fabricating an integrated circuit is disclosed. The method includes defining a via grid, generating a first layout design of the integrated circuit based on at least the via grid or design criteria, generating a standard cell layout design of the integrated circuit, generating a via color layout design of the integrated circuit based on the first layout design and the standard cell layout design, performing a color check on the via color layout design based on design rules, and fabricating the integrated circuit based on at least the via color layout design. The first layout design has a first set of vias arranged in first rows and first columns based on the via grid. The standard cell layout design has standard cells and a second set of vias arranged in the standard cells. The via color layout design has a third set of vias.

Abstract: The invention provides an LED including a first-type semiconductor layer, an emitting layer, a second-type semiconductor layer, a first electrode, a second electrode, a Bragg reflector structure, a conductive layer and insulation patterns. The first electrode and the second electrode are located on the same side of the Bragg reflector structure. The conductive layer is disposed between the Bragg reflector structure and the second-type semiconductor layer. The insulation patterns are disposed between the conductive layer and the second-type semiconductor layer. Each insulating layer has a first surface facing toward the second-type semiconductor layer, a second surface facing away from the second-type semiconductor layer, and an inclined surface. The inclined surface connects the first surface and the second surface and is inclined with respect to the first surface and the second surface.

Abstract: Optical proximity correction (OPC) based computational lithography techniques are disclosed herein for enhancing lithography printability. An exemplary mask optimization method includes receiving an integrated circuit (IC) design layout having an IC pattern; generating target points for a contour corresponding with the IC pattern based on a target placement model, wherein the target placement model is selected based on a classification of the IC pattern; and performing an OPC on the IC pattern using the target points, thereby generating a modified IC design layout. The method can further include fabricating a mask based on the modified IC design layout. The OPC can select an OPC model based on the classification of the IC pattern. The OPC model can weight the target placement model.

Abstract: Examples of optical proximity correction (OPC) based computational lithography techniques are disclosed herein. An exemplary method includes receiving an IC design layout that includes an IC feature, the IC feature specifying a mask feature for selectively exposing to radiation a portion of a photoresist disposed on a substrate; determining topographical information of an underlying layer disposed on the substrate between the photoresist and the substrate; performing an OPC process on the IC feature to generate a modified IC feature; and providing a modified IC design layout including the modified IC feature for fabricating a mask based on the modified IC design layout. The OPC process may use the topographical information of the underlying layer to compensate for an amount of radiation directed towards the portion of the photoresist so as to expose the portion of the photoresist to a target dosage of radiation.

Abstract: A method of fabricating an integrated circuit is disclosed. The method includes defining a via grid, generating a first layout design of the integrated circuit based on at least the via grid or design criteria, generating a standard cell layout design of the integrated circuit, generating a via color layout design of the integrated circuit based on the first layout design and the standard cell layout design, performing a color check on the via color layout design based on design rules, and fabricating the integrated circuit based on at least the via color layout design. The first layout design has a first set of vias arranged in first rows and first columns based on the via grid. The standard cell layout design has standard cells and a second set of vias arranged in the standard cells. The via color layout design has a third set of vias.

Abstract: The invention provides an LED including a first-type semiconductor layer, an emitting layer, a second-type semiconductor layer, a first electrode, a second electrode, a Bragg reflector structure, a conductive layer and insulation patterns. The first electrode and the second electrode are located on the same side of the Bragg reflector structure. The conductive layer is disposed between the Bragg reflector structure and the second-type semiconductor layer. The insulation patterns are disposed between the conductive layer and the second-type semiconductor layer. Each insulating layer has a first surface facing toward the second-type semiconductor layer, a second surface facing away from the second-type semiconductor layer, and an inclined surface. The inclined surface connects the first surface and the second surface and is inclined with respect to the first surface and the second surface.