Patents by Inventor Wei Chen

Wei Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240160399
    Abstract: This document describes systems and techniques for facilitating spatial rediscovery using on-device hardware. For example, an audio input mechanism associated with a compact device can be activated and an audio signal can be generated by an audio output mechanism associated with an external device. The audio signal can be received at the audio input mechanism associated with the compact device. The receipt of the audio signal may cause the audio input mechanism to produce electrical signals having encoded information associated with the audio signal. The electrical signals can then be transmitted to the external device as wireless signals. Based on an analysis of the transmitted wireless signals, a spatial positioning of the compact device relative to the external device can be determined. Based on the determination of the spatial positioning, a location indicator can be provided via the external device.
    Type: Application
    Filed: January 25, 2024
    Publication date: May 16, 2024
    Applicant: Google LLC
    Inventors: Wei Liang Liu, Pei-Chen Chuang
  • Publication number: 20240160303
    Abstract: A control method of a touchpad is provided. The touchpad has a determination module including a neural network. The determination module is used to determine the type of object. When the user uses the touchpad, the touchpad uses the captured object feature data of the touch object to update the determination module. Therefore, when determining the type of the touch object, the updated determination module can more accurately determine the touch object used by the user, so as to improve the determination accuracy.
    Type: Application
    Filed: October 31, 2023
    Publication date: May 16, 2024
    Applicant: ELAN MICROELECTRONICS CORPORATION
    Inventors: Chang-Ru CHEN, Tuan-Ying CHANG, Hsueh-Wei YANG
  • Publication number: 20240160306
    Abstract: A display panel, including an active area and a peripheral area, which is located outside of the active area, wherein the active area comprises a base substrate, and a display structure layer and a touch structure layer sequentially arranged on the base substrate; the peripheral area includes an isolation dam, a first ground trace and a second ground trace arranged on the base substrate; and the first ground trace is located at a side of the isolation dam close to the active area, and the second ground trace is located at a side of the isolation dam away from the active area.
    Type: Application
    Filed: January 9, 2023
    Publication date: May 16, 2024
    Inventors: Chang LUO, Xiping LI, Hongwei MA, Ming HU, Wei HE, Youngyik KO, Haijun QIU, Yi ZHANG, Taofeng XIE, Tianci CHEN, Qun MA, Xinghua LI, Ping WEN, Yang ZHOU, Yuanqi ZHANG, Xiaoyan YANG, Shun ZHANG, Pandeng TANG, Yang ZENG, Tong ZHANG, Xiaofei HOU, Zhidong WANG, Haoyuan FAN, Jinhwan HWANG
  • Publication number: 20240160955
    Abstract: A computer-implemented method for optimized decision making that includes labeling text data extracted from an inquiry, and linking labeled text to a knowledge graph entity. The method may further include retrieving from the knowledge graph reasoning paths; and removing irrelevant knowledge graph reasoning paths using a language model trained artificial intelligence consistent with the labeling of the text data. The method may further include employing remaining relevant graph reasoning paths to provide an answer prediction.
    Type: Application
    Filed: November 7, 2023
    Publication date: May 16, 2024
    Inventors: Xujiang Zhao, Yanchi Liu, Wei Cheng, Haifeng Chen
  • Publication number: 20240160828
    Abstract: A method of generating an IC layout diagram includes receiving an IC layout diagram including a gate region and a gate via, the gate via being positioned at a location within an active region and along a width of the gate region extending across the active region, receiving a first gate resistance value of the gate region, retrieving a second gate resistance value from a resistance value reference based on the location and the width, using the first and second resistance values to determine that the IC layout diagram does not comply with a design specification, and based on the non-compliance with the design specification, modifying the IC layout diagram.
    Type: Application
    Filed: January 24, 2024
    Publication date: May 16, 2024
    Inventors: Ke-Ying SU, Jon-Hsu HO, Ke-Wei SU, Liang-Yi CHEN, Wen-Hsing HSIEH, Wen-Koi LAI, Keng-Hua KUO, KuoPei LU, Lester CHANG, Ze-Ming WU
  • Publication number: 20240162220
    Abstract: A capacitor on a fin structure includes a fin structure. A dielectric layer covers the fin structure. A first electrode extension is embedded within the fin structure. A first electrode penetrates the dielectric layer and contacts the first electrode extension. A second electrode and a capacitor dielectric layer are disposed within the dielectric layer. The capacitor dielectric layer surrounds the second electrode, and the capacitor dielectric layer is between the second electrode and the first electrode extension.
    Type: Application
    Filed: December 8, 2022
    Publication date: May 16, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Hsin-Yu Chen, Chun-Hao Lin, Yuan-Ting Chuang, Shou-Wei Hsieh
  • Publication number: 20240162088
    Abstract: An integrated circuit device includes an interconnect layer, a memory structure, a third conductive feature, and a fourth conductive feature. The interconnect layer includes a first conductive feature and a second conductive feature. The memory structure is over and in contact with the first conductive feature. The memory structure includes at least a resistance switching element over the first conductive feature. The third conductive feature, including a first conductive line, is over and in contact with the second conductive feature. The fourth conductive feature is over and in contact with the memory structure. The fourth conductive feature includes a second conductive line, a top surface of the first conductive line is substantially level with a top surface of the second conductive line, and a bottom surface of the first conductive line is lower than a bottommost portion of a bottom surface of the second conductive line.
    Type: Application
    Filed: January 25, 2024
    Publication date: May 16, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsia-Wei CHEN, Fu-Ting SUNG, Yu-Wen LIAO, Wen-Ting CHU, Fa-Shen JIANG, Tzu-Hsuan YEH
  • Publication number: 20240163488
    Abstract: Implementations of the disclosure provide video processing apparatuses and methods. The method receives, by a video processor, a video block of a video for in-loop filtering. The method then performs a wavelet-domain CNN filtering on video data of at least a part of the video block, by performing, by the video processor, a wavelet transform on the video data to obtain data in a wavelet domain comprising a plurality of wavelet subbands; filtering, by the video processor, the data in the wavelet domain by applying respective CNN models on the plurality of wavelet subbands, where the CNN models for the plurality of wavelet subbands are trained in the wavelet domain; and performing, by the video processor, an inverse wavelet transform on the filtered data to obtain reconstructed video data.
    Type: Application
    Filed: January 23, 2024
    Publication date: May 16, 2024
    Applicant: Beijing Dajia Internet Information Technology Co. Ltd.
    Inventors: Ning Yan, Wei Chen, Xiaoyu Xiu, Che-Wei Kuo, Yi-Wen Chen, Hong-Jheng Jhu, Xianglin Wang, Bing Yu
  • Publication number: 20240162051
    Abstract: Some implementations described herein include systems and techniques for fabricating a stacked die product. The systems and techniques include using a supporting fill mixture that includes a combination of types of composite particulates in a lateral gap region of a stack of semiconductor substrates and along a perimeter region of the stack of semiconductor substrates. One type of composite particulate included in the combination may be a relatively smaller size and include a smooth surface, allowing the composite particulate to ingress deep into the lateral gap region. Properties of the supporting fill mixture including the combination of types of composite particulates may control thermally induced stresses during downstream manufacturing to reduce a likelihood of defects in the supporting fill mixture and/or the stack of semiconductor substrates.
    Type: Application
    Filed: April 27, 2023
    Publication date: May 16, 2024
    Inventors: Kuo-Ming WU, Hau-Yi HSIAO, Kai-Yun YANG, Che Wei YANG, Sheng-Chau CHEN, Chung-Yi YU, Cheng-Yuan TSAI
  • Publication number: 20240164043
    Abstract: A swivel bracket assembly and a method for installing an electrical component to a riser bracket assembly are disclosed. The swivel bracket assembly includes a baseplate; a swivel bracket rotatably attached to the baseplate, the swivel bracket being rotatable between an open position and a closed position; and pads attached to the swivel bracket, at least one of the pads being configured to contact and support the electrical component attached to the riser bracket assembly when the swivel bracket is in the closed position. A method for installing an electrical component to a riser bracket assembly includes receiving the electrical component into a slot of a riser circuit board and pivoting a swivel bracket rotatable coupled to a baseplate from an open position to a closed position to support the electrical component secured to the riser bracket assembly.
    Type: Application
    Filed: November 14, 2022
    Publication date: May 16, 2024
    Inventors: Yaw-Tzorng TSORNG, Ming-Lung WANG, Hung-Wei CHEN, Liang-Ju LIN
  • Publication number: 20240163072
    Abstract: The present disclosure provides a calibration method and readable computer storage medium. The calibration method includes: configuring a reference signal source to output a reference signal; delaying the reference signal through a delay chain to output a delay signal; synchronous sampling the reference signal and the delay signal; adding 1 count and obtaining a final count value when the sampling result is in the preset state; determining whether a ratio between the count value and the first quantity is within a preset range; obtaining the average delay time according to the time width of the reference signal wave and the number of the delay units opened in the delay chain when the ratio is within the preset range; and outputting a control signal to the clock recovery circuit according to the average delay time to calibrate the delay time of the clock recovery circuit.
    Type: Application
    Filed: February 2, 2023
    Publication date: May 16, 2024
    Inventors: YU-CHIEH HSU, LING-WEI KE, CHUN-YU CHEN, HONG-YUN WEI
  • Patent number: 11983220
    Abstract: A URL and a categorization associated with the URL are received. The received URL comprises a hostname portion and a path portion. The hostname portion of the received URL comprises a plurality of segments separated by one or more delimiters. A key associated with the received URL is determined. An operation is performed on a database using the determined key. Examples of such operations include inserting the categorization into the database, changing a value associated with the key in the database, removing a key-value pair from the database, and querying the database.
    Type: Grant
    Filed: November 30, 2022
    Date of Patent: May 14, 2024
    Assignee: Palo Alto Networks, Inc.
    Inventors: Wei Cao, Dao-Chen Zheng
  • Patent number: 11985132
    Abstract: A method of providing continuous user authentication for resource access control includes launching a continuous authentication service at a boot time of a first device, wherein the first device includes a processor, a memory, and one or more sensors configured to collect authentication information. Additionally, the method includes receiving authentication information comprising one or more of explicit authentication information or implicit authentication information, and receiving a request for access to a resource of the first device. Further, the method includes the operations of determining, by the continuous authentication service, a current value of a security state, the current value of the security state based in part on a time interval between a receipt time of the authentication information and a current time and controlling access to the resource based on the current value of the security state.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: May 14, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Haining Chen, Xun Chen, Khaled ElWazeer, Ahmed M. Azab, David Thomson, Ruowen Wang, Wei Yang, Peng Ning
  • Patent number: 11983482
    Abstract: A system and method for converting a document is described. The system accesses a document comprising one or more section breaks. The system detects sections of the text document demarked by the one or more section breaks and generates a section title metadata and a section summary metadata for each section of the plurality of sections. The system inserts the section title metadata and the section summary metadata at the corresponding section breaks in the text document. The system modifies the text document into slides. Each slide being formed for each section based on the corresponding section title metadata and the section summary metadata. The system generates a presentation document based on the slides.
    Type: Grant
    Filed: May 20, 2021
    Date of Patent: May 14, 2024
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Tomasz Lukasz Religa, Utsab Bose, Si-Qing Chen, Lei Cui, Tao Ge, Huitian Jiao, Ravi Mandliya, Kaushik Ramaiah Narayanan, Max Wang, Furu Wei
  • Patent number: 11985324
    Abstract: Exemplary video processing methods and apparatuses for encoding or decoding a current block by inter prediction are disclosed. Input data of a current block is received and partitioned into sub-partitions and motion refinement is independently performed on each sub-partition. A reference block for each sub-partition is obtained from one or more reference pictures according to an initial motion vector (MV). A refined MV for each sub-partition is derived by searching around the initial MV with N-pixel refinement. One or more boundary pixels of the reference block for a sub-partition is padded for motion compensation of the sub-partition. A final predictor for the current block is generated by performing motion compensation for each sub-partition according to its refined MV. The current block is then encoded or decoded according to the final predictor.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: May 14, 2024
    Assignee: HFI INNOVATION INC.
    Inventors: Yu-Cheng Lin, Chun-Chia Chen, Chih-Wei Hsu, Ching-Yeh Chen, Tzu-Der Chuang, Yu-Wen Huang
  • Patent number: 11984558
    Abstract: The disclosure provides a button-type lithium ion battery and a method for fabricating the same. The lithium ion battery includes a shell, a winding core, a center upright, a pole and tabs, wherein the shell is internally provided with a cavity, the winding core is arranged in the cavity, at least one end of the center upright is provided with an opening, the pole is arranged on the shell, the tabs are connected with the winding core, and the tabs extend to the inside of the opening and are electrically connected with the pole. According to the disclosure, the relatively thick pole is electrically connected with the winding core and then embedded into the center uptight so that the space inside the center upright is sufficiently utilized, the whole thickness of the shell is reduced and the utilization space of the battery is increased.
    Type: Grant
    Filed: June 20, 2020
    Date of Patent: May 14, 2024
    Assignee: ZHONGSHAN ZHONGWANGDE NEW ENERGY TECHNOLOGY CO., LTD
    Inventors: Wei Chen, Xuehua Huang
  • Patent number: 11981616
    Abstract: A method for preparing 3,3?-diaminobenzidine, the method comprising the following steps: subjecting 4,4?-biphenol and N,N-dimethylsulfamoyl chloride to an esterification reaction in a specified solvent at 40-70° C. to obtain 4,4?-biphenyl bis(N,N-dimethylaminosulfonate) as a first intermediate; subjecting the 4,4?-biphenyl bis(N,N-dimethylaminosulfonate) to a chlorination reaction with a chlorinating reagent under acidic conditions to obtain 3,3?-dichloro-4,4?-biphenyl bis(N,N-dimethylaminosulfonate) as a second intermediate; subjecting the second intermediate 3,3?-dichloro-4,4?-biphenyl bis(N,N-dimethylaminosulfonate) to an ammonolysis reaction with anammoniation reagent in the presence of a combined catalyst to obtain a crude product of 3,3?,4,4?-tetraaminobiphenyl, wherein the combined catalyst is a mixture of proline, a cuprous salt and a phase transfer catalyst; and subjecting the crude product of 3,3?,4,4?-tetraaminobiphenyl to a post-treatment to obtain a purified 3,3?,4,4?-tetraaminobiphenyl product.
    Type: Grant
    Filed: January 12, 2022
    Date of Patent: May 14, 2024
    Assignees: Hubei Huida High-Tech Co., Ltd, Borun High-Tech Co., Ltd.
    Inventors: Yun Ling, Yongfang Li, Kun Wang, Lizhu Chen, Wei Yin, Jinying Zhang
  • Patent number: 11983848
    Abstract: Aspects of the disclosure provide a frame processor for processing frames with aliasing artifacts. For example, the frame processor can include a super-resolution (SR) and anti-aliasing (AA) engine and an attention reference frame generator coupled to the SR and AA engine. The SR and AA engine can be configured to enhance resolution and remove aliasing artifacts of a frame to generate a first high-resolution frame with aliasing artifacts and a second high-resolution frame with aliasing artifacts removed. The attention reference frame generator can be configured to generate an attention reference frame based on the first high-resolution frame and the second high-resolution frame.
    Type: Grant
    Filed: January 6, 2023
    Date of Patent: May 14, 2024
    Assignee: MEDIATEK INC.
    Inventors: Cheng-Lung Jen, Pei-Kuei Tsung, Chih-Wei Chen, Yao-Sheng Wang, Shih-Che Chen, Yu-Sheng Lin, Chih-Wen Goo, Shih-Chin Lin, Tsung-Shian Huang, Ying-Chieh Chen
  • Patent number: 11981811
    Abstract: Provided are a use of a thermoplastic polyurethane for forming an impact resistant layer and an impact resistant composite laminate. The thermoplastic polyurethane comprises a structural unit represented by Formula (I): wherein each R independently is an alkylene group having 2 to 8 carbon atoms or CH2CH2OCH2CH2; n is a number from 2 to 13; and the structural unit has a Mn ranging from 700 g/mole to 2500 g/mole. In addition, the impact resistant layer has a thickness of larger than 1.5 mm. The impact resistant composite laminate comprises a base layer and the impact resistant layer disposed on the base layer.
    Type: Grant
    Filed: March 8, 2022
    Date of Patent: May 14, 2024
    Assignee: SUNKO INK CO., LTD.
    Inventors: Chiu-Peng Tsou, Zhen-Wei Chen, Ting-Ti Huang, Sheng-Mao Tseng
  • Patent number: D1026910
    Type: Grant
    Filed: November 7, 2023
    Date of Patent: May 14, 2024
    Assignee: HTC CORPORATION
    Inventors: Shu-Kuen Chang, Natalia Amijo, Ian James McGillivray, Chin-Wei Chou, Yi-Shen Wang, Chih-Sung Fang, Hung-Yu Chen