Patents by Inventor Wei Cheng

Wei Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240154447
    Abstract: A power system including a first battery pack, a second battery pack, and a power management circuit is disclosed. The first battery pack has a first end and a second end, and has a first battery capacity. The second battery pack has a third end and a fourth end. The third end is coupled to the second end of the first battery pack and provides a low battery voltage. The fourth end is grounded, the second battery pack has a second battery capacity, and the second battery capacity is greater than the first battery capacity. The power management circuit is coupled to the second battery pack to receive the low battery voltage, and provides a component operating voltage to an electronic components based on the low battery voltage.
    Type: Application
    Filed: August 29, 2023
    Publication date: May 9, 2024
    Applicant: PEGATRON CORPORATION
    Inventors: Yi-Hsuan Lee, Liang-Cheng Kuo, Chun-Wei Ko, Ya Ju Cheng, Chih Wei Huang, Ywh Woei Yeh, Yu Cheng Lin, Yen Ting Wang
  • Publication number: 20240153896
    Abstract: A first protective layer is formed on a first die and a second die, and openings are formed within the first protective layer. The first die and the second die are encapsulated such that the encapsulant is thicker than the first die and the second die, and vias are formed within the openings. A redistribution layer can also be formed to extend over the encapsulant, and the first die may be separated from the second die.
    Type: Application
    Filed: January 12, 2024
    Publication date: May 9, 2024
    Inventors: Hui-Min Huang, Chih-Wei Lin, Tsai-Tsung Tsai, Ming-Da Cheng, Chung-Shi Liu, Chen-Hua Yu
  • Publication number: 20240154191
    Abstract: The present application provides a flow test tool, a negative pressure formation apparatus, and a battery manufacturing device. The flow test tool includes a base and a flow test module mounted on the base, the flow test module is provided with a plurality of test interfaces, and the test interface is connected to a fluid channel of a mechanism to be tested one by one.
    Type: Application
    Filed: September 22, 2023
    Publication date: May 9, 2024
    Inventors: Shaosheng Cheng, Wen Yu, Jiefei Gong, Fengyu Guo, Yanqing Chen, Wei Wang, Weidong Song, Shaohui Zhang, Gege Chen
  • Publication number: 20240155260
    Abstract: A pixel array includes a plurality of dark pixel sensors configured to generate dark current calibration information for a plurality of visible light pixel sensors included in the pixel array. The plurality of dark pixel sensors may generate respective dark current measurements for each of the plurality of visible light pixel sensors or for small subsets of the plurality of visible light pixel sensors. In this way, each of the plurality of visible light pixel sensors may be individually calibrated (or small subsets of the plurality of visible light pixel sensors may be individually calibrated) based on an estimated dark current experienced by each of the plurality of visible light pixel sensors. This may enable more accurate dark current calibration of the visible light pixel sensors included in the pixel array, and may be used to account for large differences in estimated dark currents for the visible light pixel sensors.
    Type: Application
    Filed: January 18, 2024
    Publication date: May 9, 2024
    Inventors: Feng-Chien HSIEH, Yun-Wei CHENG, Kuo-Cheng LEE
  • Publication number: 20240153979
    Abstract: A method of manufacturing an image sensor structure includes forming an isolation structure in a substrate to divide the substrate into a first region and a second region, forming a first light sensing region in the first region and a second light sensing region in the second region, forming a first gate structure over the first light sensing region and a second gate structure over the second light sensing region, forming gate spacers on sidewalls of the first and second gate structures, and depositing a blocking layer on sidewalls of the gate spacers. The blocking layer has an opening positioned between the first and second gate structures. A source/drain structure is formed directly under the opening in the blocking layer. The method also includes forming an interlayer dielectric layer over the first and second gate structures and the blocking layer.
    Type: Application
    Filed: April 13, 2023
    Publication date: May 9, 2024
    Inventors: Wei Long CHEN, Wen-I HSU, Feng-Chi HUNG, Jen-Cheng LIU, Dun-Nian YAUNG
  • Publication number: 20240154022
    Abstract: A method for manufacturing a semiconductor device includes forming a first fin structure and a second fin structure, wherein an isolation region is located between the fin structures, and wherein a space is located between the fin structures and above the isolation region; depositing a blocking layer over the first fin structure, the isolation region, and the second fin structure, wherein an upper portion of the blocking layer is located above the first fin structure and the second fin structure, and wherein a lower portion of the blocking layer fills the space located between the first fin structure and the second fin structure; removing the upper portion of the blocking layer; and while the lower portion of the blocking layer remains over the isolation region, performing an etch process to recess the first fin structure and the second fin structure.
    Type: Application
    Filed: February 7, 2023
    Publication date: May 9, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Chieh Ho, Po-Cheng Wang, De-Fang Chen, Chao-Cheng Chen
  • Publication number: 20240153824
    Abstract: A method includes forming a stack of channel layers and sacrificial layers over a substrate, patterning the stack to form a fin-shape structure, and recessing a portion of the fin-shape structure to form a recess. A top surface of the substrate under the recess is covered at least by a bottommost sacrificial layer of the stack. The method also includes forming inner spacers on terminal ends of the sacrificial layers that are above the bottommost sacrificial layer, depositing an undoped layer in the recess, and forming a doped epitaxial feature over the undoped layer. The undoped layer covers terminal ends of a bottommost channel layer of the stack. The doped epitaxial feature covers terminal ends of the channel layers that are above the bottommost channel layer.
    Type: Application
    Filed: March 22, 2023
    Publication date: May 9, 2024
    Inventors: Ting-Yeh CHEN, Wei-Yang LEE, Po-Cheng WANG, De-Fang CHEN, Chao-Cheng CHEN
  • Publication number: 20240153257
    Abstract: A monitoring system based on a digital converter station includes a first monitoring terminal deployed at a first-level monitoring side, a second monitoring terminal deployed at a second-level monitoring side, and a third monitoring terminal deployed at a third-level monitoring side; the monitoring terminal at each level includes a communication module, a human-machine interaction module, a device status monitoring module, a device alarm management module, a video fusion processing module, and a data transmission adjustment and control module.
    Type: Application
    Filed: January 11, 2024
    Publication date: May 9, 2024
    Applicants: STATE GRID CORPORATION OF CHINA, STATE GRID ECONOMIC AND TECHNOLOGICAL RESEARCH INSTITUTE CO., LTD, NR ELECTRIC CO., LTD., XJ GROUP CORPORATION, NARI TECHNOLOGY CO., LTD, BEIJING SGITG ACCENTURE INFORMATION TECHNOLOGY CENTER CO., LTD., HUAWEI TECHNOLOGY CO., LTD
    Inventors: Wei JIN, Qing WANG, Xianshan GUO, Jun LYU, Siyuan LIU, Xiang ZHANG, Yanguo WANG, Zhanguo ZHANG, Haifeng WANG, Chong TONG, Ming LI, Wei CHENG, Ning ZHAO, Zhou CHEN, Xiaojun HOU, Hanqing ZHAO
  • Publication number: 20240153895
    Abstract: Semiconductor dies of a semiconductor die package are directly bonded, and a top metal region may be formed over the semiconductor dies. A plurality of conductive terminals may be formed over the top metal region. The conductive terminals are formed of copper (Cu) or another material that enables low-temperature deposition process techniques, such as electroplating, to be used to form the conductive terminal. In this way, the conductive terminals of the semiconductor die packages described herein may be formed at a relatively low temperature. This reduces the likelihood of thermal deformation of semiconductor dies in the semiconductor die packages. The reduced thermal deformation reduces the likelihood of warpage, breakage, and/or other types of damage to the semiconductor dies of the semiconductor die packages, which may increase performance and/or increase yield of semiconductor die packages.
    Type: Application
    Filed: April 19, 2023
    Publication date: May 9, 2024
    Inventors: Harry-HakLay CHUANG, Wei-Cheng WU, Chung-Jen HUANG, Yung Chun TU, Chien Lin LIU, Shun-Kuan LIN, Ping-tzu CHEN
  • Publication number: 20240152880
    Abstract: A multi-channel payment method for a multi-channel payment system comprises the payer or the payee who initiated the payment request logs in to the multi-channel payment system; the payer or the payee who initiated the payment request placing an order in the multi-channel payment system, wherein the order comprises a designated payment gateway; the multi-channel payment system determining a predicted fee of the order according to the designated payment gateway, past order records, and a real-time exchange rate; the multi-channel payment system performing an anti-money laundering verification of the order; the payer reviewing the order and the predicted fee through a multiple auditing method; and the multi-channel payment system executing payment from the payer to the payee according to the order and the designated payment gateway, and storing a payment detail of the order.
    Type: Application
    Filed: February 13, 2023
    Publication date: May 9, 2024
    Applicant: OBOOK INC.
    Inventors: Chun-Kai Wang, Chung-Han Hsieh, Chun-Jen Chen, Po-Hua Lin, Wei-Te Lin, Pei-Hsuan Weng, Mei-Su Wang, I-Cheng Lin, Cheng-Wei Chen
  • Publication number: 20240148301
    Abstract: The present invention provides a smart wearable device, which is held on an upper body of a wearer by a plurality of contact pad sets, and has a connection unit, a first sensing module, a second sensing module, and an extension unit.
    Type: Application
    Filed: November 7, 2022
    Publication date: May 9, 2024
    Inventors: Chien-Hsiang Chang, Yang-Cheng Lin, Wei-Chih Lien, Tseng-Ping Chiu, Pei-Yun Wu, Bo Liu
  • Publication number: 20240150942
    Abstract: The present application discloses a warp knitting traverse device and a warp knitting machine. The warp knitting traverse device includes a faceplate and a comb. The cross-section of the faceplate is an annular shape with different outer diameters, and the annular shape is divided into x number of equal parts, courses, along the circumferential direction and wherein 2?x?8; on the outer surface of the faceplate, at least two slopes are formed between adjacent courses. The present invention utilizes this new structural design, and designs a gradually gentle slope for buffering for the comb movement, allowing the comb to move step by step, which can avoid the instability caused by sudden large span, and is conducive to achieve high precision and smoothness in using a warp knitting machine in the process of fabric production. The new improvement preserve the machine for continuous production and achieve high throughput.
    Type: Application
    Filed: November 5, 2022
    Publication date: May 9, 2024
    Applicant: Sumec Textile Technology Co., Ltd.
    Inventors: Long Cheng, Wei Chen
  • Patent number: 11976374
    Abstract: A method and device of removing and recycling metals from a mixing acid solution, includes adsorbing a mixing acid solution with a pH value of ?1 to 4 and a cobalt ion concentration of 100 to 1,000 mg/L by at least two cation resins in series setting to the cobalt ion concentration in the mixing acid solution is less than 10 mg/L, and then adjusting the pH value of the mixing acid solution after adsorption to meet a discharge standard, wherein the particle size of the at least two cation resins in series setting is 150˜1,200 ?m. After the cation resins are saturated by adsorption, regenerating the cation resins by sulfuric acid to form a cobalt sulfate solution, and then electrolytically treating the cobalt sulfate solution to obtain electrolytic cobalt and sulfuric acid electrolyte. The operation process is simple without complicated equipment, and it can effectively recycle metals from mixing acid solutions.
    Type: Grant
    Filed: September 10, 2020
    Date of Patent: May 7, 2024
    Assignee: MEGA UNION TECHNOLOGY INCORPORATED
    Inventors: Kuo-Ching Lin, Yung-Cheng Chiang, Shr-Han Shiu, Wei-Rong Tey, Yu-Hsuan Li
  • Patent number: 11978740
    Abstract: A layer stack including a first bonding dielectric material layer, a dielectric metal oxide layer, and a second bonding dielectric material layer is formed over a top surface of a substrate including a substrate semiconductor layer. A conductive material layer is formed by depositing a conductive material over the second bonding dielectric material layer. The substrate semiconductor layer is thinned by removing portions of the substrate semiconductor layer that are distal from the layer stack, whereby a remaining portion of the substrate semiconductor layer includes a top semiconductor layer. A semiconductor device may be formed on the top semiconductor layer.
    Type: Grant
    Filed: February 17, 2022
    Date of Patent: May 7, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Harry-Hak-Lay Chuang, Kuo-Ching Huang, Wei-Cheng Wu, Hsin Fu Lin, Henry Wang, Chien Hung Liu, Tsung-Hao Yeh, Hsien Jung Chen
  • Patent number: 11978782
    Abstract: The present disclosure relates to a hybrid integrated circuit. In one implementation, an integrated circuit may have a first region with a first gate structure having a ferroelectric gate dielectric, at least one source associated with the first gate of the first region, and at least one drain associated with the first gate structure of the first region. Moreover, the integrated circuit may have a second region with a second gate structure having a high-? gate dielectric, at least one source associated with the second gate structure of the second region, and at least one drain associated with the second gate structure of the second region. The integrated circuit may further have at least one trench isolation between the first region and the second region.
    Type: Grant
    Filed: June 9, 2022
    Date of Patent: May 7, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chi-Yi Chuang, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 11977335
    Abstract: A pattern decomposition method including following steps is provided. A target pattern is provided, wherein the target pattern includes first patterns and second patterns alternately arranged, and the width of the second pattern is greater than the width of the first pattern. Each of the second patterns is decomposed into a third pattern and a fourth pattern, wherein the third pattern and the fourth pattern have an overlapping portion, and a pattern formed by overlapping the third pattern and the fourth pattern is the same as the second pattern. The third patterns and the first pattern adjacent to the fourth pattern are designated as first photomask patterns of a first photomask. The fourth patterns and the first pattern adjacent to the third pattern are designated as second photomask patterns of a second photomask.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: May 7, 2024
    Assignee: United Microelectronics Corp.
    Inventors: Min Cheng Yang, Wei Cyuan Lo, Yung-Feng Cheng
  • Patent number: 11974711
    Abstract: The present disclosure discloses a dish washer. The dish washer includes a container, a spraying duct, and a water supply system. The container has a cleaning area therein. A plurality of spraying devices are provided, and each spraying device is provided with a spraying hole and has a water inflow end. The water supply system is in communication with a water supply and the water inflow end of the spraying device. According to the dish washer of the present disclosure, water spray can be individually controlled by the multiple water supply systems or by cooperation between one water supply system and the diverter valve. Thus, the dish washer has satisfactory water usage efficiency.
    Type: Grant
    Filed: June 19, 2020
    Date of Patent: May 7, 2024
    Assignees: FOSHAN SHUNDE MIDEA WASHING APPLIANCES MANUFACTURING CO., LTD., MIDEA GROUP CO., LTD.
    Inventors: Wei Zhang, Siqi Cai, Fanhua Cheng, Weijun Xue
  • Patent number: 11978678
    Abstract: A display device includes a first substrate, a light-emitting element, a light conversion layer, and a color filter layer. The light-emitting element is disposed on the first substrate. The light conversion layer is disposed on the light-emitting element. In addition, the color filter layer is overlapped the light-emitting element and the light conversion layer.
    Type: Grant
    Filed: August 5, 2022
    Date of Patent: May 7, 2024
    Assignee: INNOLUX CORPORATION
    Inventors: Tung-Kai Liu, Tsau-Hua Hsieh, Wei-Cheng Chu, Chun-Hsien Lin, Chandra Lius, Ting-Kai Hung, Kuan-Feng Lee, Ming-Chang Lin, Tzu-Min Yan, Hui-Chieh Wang
  • Publication number: 20240143791
    Abstract: The invention introduces an apparatus for detecting errors during data encryption. The apparatus includes a search circuitry and a substitution check circuitry. The key generation circuitry is arranged operably to convert a first value of one byte corresponding to a plaintext, an intermediate encryption result, or a round key into a second value of a K-bit according to an 8-to-K lookup table, where K is an integer ranging from 10 to 15 and the second value comprises (K minus 8) bits of a Hamming parity. The substitution check circuitry is arranged operably to employ check formulae corresponding to the 8-to-K lookup table to determine whether an error is occurred during a conversion of the first value of the one byte into the second value of the K-bit, and output an error signal when finding the error, where a total amount of the formulae is K minus 8.
    Type: Application
    Filed: May 30, 2023
    Publication date: May 2, 2024
    Applicant: Silicon Motion, Inc.
    Inventors: Wun-Jhe WU, Po-Hung CHEN, Chiao-Wen CHENG, Jiun-Hung YU, Chih-Wei LIU
  • Publication number: 20240141388
    Abstract: The present invention relates to variant polypeptides, methods of preparing the variant polypeptides, processes for characterizing the variant polypeptides, compositions and cells comprising the variant polypeptides, and methods of using the variant polypeptides. The invention further relates to complexes comprising the variant polypeptides, methods of producing the complexes, processes for characterizing the complexes, cells comprising the complexes, and methods of using the complexes.
    Type: Application
    Filed: March 9, 2022
    Publication date: May 2, 2024
    Inventors: Shaorong Chong, Wei-Cheng Lu, Brendan Jay Hilbert, Quinton Norman Wessells, Lauren E. Alfonse, Anthony James Garrity