Patents by Inventor Wei-Chi Lee
Wei-Chi Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240158309Abstract: The invention provides a material surface treatment equipment, which is applied to a material substrate. The material surface treatment equipment includes a surface treatment device and at least one waveguide device. The surface treatment device is used to carry the material substrate to perform a surface treatment process. Each waveguide device is used for introducing electromagnetic waves to the material substrate to assist in performing the surface treatment process. Through the introduction of electromagnetic waves, the surface treatment process of the material substrate is easy to perform and can achieve the strengthening effect.Type: ApplicationFiled: December 15, 2022Publication date: May 16, 2024Inventors: TIEN-HSI LEE, JUN-HUANG WU, YU-SHENG CHIOU, SHU-CHENG LI, WEI-CHI HUANG, HSIN CHEN
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Patent number: 11502088Abstract: A layout pattern of static random access memory at least includes a substrate, a plurality of fin structures on the substrate, a plurality of gate structures on the substrate and spanning the fin structures to form a plurality of transistors distributed on the substrate, the plurality of transistors include, a first pull-up transistor PU1, a first pull-down transistor PD1, a second pull-up transistor PU2, a second pull-down transistor PD2, a first pass gate transistor PG1, a second pass gate transistor PG2, a first read transistor RPD and a second read transistor RPG, and an additional fin structure, the additional fin structure is located between the fin structure of the first pass gate transistor PG1 and the fin structure of the second read transistor RPG.Type: GrantFiled: February 1, 2021Date of Patent: November 15, 2022Assignee: UNITED MICROELECTRONICS CORP.Inventors: Wei-Chi Lee, Shu-Wei Yeh, Chang-Hung Chen
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Publication number: 20220216220Abstract: A layout pattern of static random access memory at least includes a substrate, a plurality of fin structures on the substrate, a plurality of gate structures on the substrate and spanning the fin structures to form a plurality of transistors distributed on the substrate, the plurality of transistors include, a first pull-up transistor PU1, a first pull-down transistor PD1, a second pull-up transistor PU2, a second pull-down transistor PD2, a first pass gate transistor PG1, a second pass gate transistor PG2, a first read transistor RPD and a second read transistor RPG, and an additional fin structure, the additional fin structure is located between the fin structure of the first pass gate transistor PG1 and the fin structure of the second read transistor RPG.Type: ApplicationFiled: February 1, 2021Publication date: July 7, 2022Inventors: Wei-Chi Lee, Shu-Wei Yeh, Chang-Hung Chen
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Patent number: 10522551Abstract: A semiconductor device includes a first circuit structure and a second circuit structure. The first circuit structure has a first line terminal. The second circuit structure has a second line terminal. The first line terminal and the second line terminal are formed in a first circuit layer but separated by a gap. A conductive structure is forming in a second circuit layer above or below the first circuit layer, to electrically connect the first line terminal and the second line terminal.Type: GrantFiled: January 30, 2018Date of Patent: December 31, 2019Assignee: United Microelectronics Corp.Inventors: Chun-Hsien Huang, Ching-Cheng Lung, Yu-Tse Kuo, Chang-Hung Chen, Shu-Ru Wang, Wei-Chi Lee, Chun-Yen Tseng
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Patent number: 10504788Abstract: An inverter structure includes a first fin structure and a second fin structure respectively disposed within a P-type transistor region and an N-type transistor region on a substrate. Agate line is disposed on the substrate. A first end of the gate line is within the P-type transistor region, and a second end of the gate line is within the N-type transistor region. Two dummy gate lines are disposed at two sides of the gate line. Each dummy gate line has a third end within the P-type transistor region, and a fourth end within the N-type transistor region. A distance between the first end and the first fin structure is greater than a distance between the third end and the first fin structure. The distance between the second end and the second fin structure is smaller than a distance between the fourth end and the second fin structure.Type: GrantFiled: March 10, 2019Date of Patent: December 10, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventors: Wei-Chi Lee, Han-Tsun Wang, Chang-Hung Chen, Po-Yu Yang, Mei-Ying Fan, Mu-Kai Tsai, Guan-Shyan Lin, Tsz-Hui Kuo, Cheng-Hsiung Chen
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Publication number: 20190318964Abstract: An inverter structure includes a first fin structure and a second fin structure respectively disposed within a P-type transistor region and an N-type transistor region on a substrate. Agate line is disposed on the substrate. A first end of the gate line is within the P-type transistor region, and a second end of the gate line is within the N-type transistor region. Two dummy gate lines are disposed at two sides of the gate line. Each dummy gate line has a third end within the P-type transistor region, and a fourth end within the N-type transistor region. A distance between the first end and the first fin structure is greater than a distance between the third end and the first fin structure. The distance between the second end and the second fin structure is smaller than a distance between the fourth end and the second fin structure.Type: ApplicationFiled: March 10, 2019Publication date: October 17, 2019Inventors: Wei-Chi Lee, Han-Tsun Wang, Chang-Hung Chen, Po-Yu Yang, Mei-Ying Fan, Mu-Kai Tsai, Guan-Shyan Lin, Tsz-Hui Kuo, Cheng-Hsiung Chen
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Patent number: 10396064Abstract: The present invention provides a layout pattern of a static random access memory (SRAM). The layout pattern includes a first inverter and a second inverter constituting a latch circuit, wherein the latch circuit includes four transistors, a first access transistor (PG1) and a second access transistor (PG2) being electrically connected to the latch circuit, wherein the first access transistor is electrically connected to a first word line and a first bit line, and the second access transistor is electrically connected to a second word line and a second bit line, the first access transistor has a first gate length, the first access transistor has a second gate length, and the first gate length is different from the second gate length, and two read transistors series connected to each other, wherein one of the two read transistors is connected to the latch circuit.Type: GrantFiled: October 25, 2018Date of Patent: August 27, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventors: Jun-Jie Wang, Yu-Lin Wang, Tzu-Feng Chang, Wei-Chi Lee
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Publication number: 20190206879Abstract: A semiconductor device includes a first circuit structure and a second circuit structure. The first circuit structure has a first line terminal. The second circuit structure has a second line terminal. The first line terminal and the second line terminal are formed in a first circuit layer but separated by a gap. A conductive structure is forming in a second circuit layer above or below the first circuit layer, to electrically connect the first line terminal and the second line terminal.Type: ApplicationFiled: January 30, 2018Publication date: July 4, 2019Applicant: United Microelectronics Corp.Inventors: Chun-Hsien Huang, Ching-Cheng Lung, Yu-Tse Kuo, Chang-Hung Chen, Shu-Ru Wang, Wei-Chi Lee, Chun-Yen Tseng
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Patent number: 10276446Abstract: An inverter structure includes a first fin structure and a second fin structure respectively disposed within a P-type transistor region and an N-type transistor region on a substrate. A gate line is disposed on the substrate. A first end of the gate line is within the P-type transistor region, and a second end of the gate line is within the N-type transistor region. Two dummy gate lines are disposed at two sides of the gate line. Each dummy gate line has a third end within the P-type transistor region, and a fourth end within the N-type transistor region. A distance between the first end and the first fin structure is greater than a distance between the third end and the first fin structure. The distance between the second end and the second fin structure is smaller than a distance between the fourth end and the second fin structure.Type: GrantFiled: May 10, 2018Date of Patent: April 30, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventors: Wei-Chi Lee, Han-Tsun Wang, Chang-Hung Chen, Po-Yu Yang, Mei-Ying Fan, Mu-Kai Tsai, Guan-Shyan Lin, Tsz-Hui Kuo, Cheng-Hsiung Chen
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Publication number: 20190067268Abstract: The present invention provides a layout pattern of a static random access memory (SRAM). The layout pattern includes a first inverter and a second inverter constituting a latch circuit, wherein the latch circuit includes four transistors, a first access transistor (PG1) and a second access transistor (PG2) being electrically connected to the latch circuit, wherein the first access transistor is electrically connected to a first word line and a first bit line, and the second access transistor is electrically connected to a second word line and a second bit line, the first access transistor has a first gate length, the first access transistor has a second gate length, and the first gate length is different from the second gate length, and two read transistors series connected to each other, wherein one of the two read transistors is connected to the latch circuit.Type: ApplicationFiled: October 25, 2018Publication date: February 28, 2019Inventors: Jun-Jie Wang, Yu-Lin Wang, Tzu-Feng Chang, Wei-Chi Lee
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Patent number: 10177132Abstract: A layout pattern of a static random access memory, including a first inverter and a second inverter constituting a latch circuit. A first inner access transistor, a second inner access transistor, a first outer access transistor and a second outer access transistor are electrically connected to the latch circuit, wherein the first outer access transistor has a first gate length, the first inner access transistor has a second gate length, and the first gate length is different from the second gate length.Type: GrantFiled: April 1, 2016Date of Patent: January 8, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventors: Jun-Jie Wang, Yu-Lin Wang, Tzu-Feng Chang, Wei-Chi Lee
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Patent number: 9871047Abstract: A semiconductor structure includes a SRAM cell having transistors defined by fins and metal gate stack structures. A transistor and a corresponding pick up cell are disposed in an extension direction of the fins. The transistor and the corresponding pick up cell have metal gate stack structures of the same type.Type: GrantFiled: January 20, 2017Date of Patent: January 16, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yu-Lin Wang, Wei-Chi Lee
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Publication number: 20170243861Abstract: A layout pattern of a static random access memory, including a first inverter and a second inverter constituting a latch circuit. A first inner access transistor, a second inner access transistor, a first outer access transistor and a second outer access transistor are electrically connected to the latch circuit, wherein the first outer access transistor has a first gate length, the first inner access transistor has a second gate length, and the first gate length is different from the second gate length.Type: ApplicationFiled: April 1, 2016Publication date: August 24, 2017Inventors: Jun-Jie Wang, Yu-Lin Wang, Tzu-Feng Chang, Wei-Chi Lee
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Patent number: 9455202Abstract: A mask set includes a first mask and a second mask. The first mask includes geometric patterns. The second mask includes at least a strip-shaped pattern with a first edge and a second edge opposite to the first edge. The strip-shaped pattern has a centerline along a long axis of the strip-shaped pattern. The first edge includes inwardly displaced segments shifting towards the centerline and each of the inwardly displaced segments overlaps each of the geometric patterns.Type: GrantFiled: May 29, 2014Date of Patent: September 27, 2016Assignee: UNITED MICROELECTRONICS CORP.Inventors: Wei-Chi Lee, Yu-Lin Wang, Chung-Yuan Lee
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Publication number: 20160099184Abstract: A method of estimating the capability of a semiconductor manufacturing system is provided. Plural first transistors are formed and a first VtMM value and a first scale value are obtained. Plural second transistors are formed and a second VtMM value and a second scale value are obtained. Plural third transistors are formed and a third VtMM value and a third scale value are obtained. A first channel length of the first transistor is smaller than a second channel length of the second transistor and is equal to a third channel length of the third transistor. A VtMM v.s. scale figure is established. A line is formed by linking the first dot and the third dot and a vertical Gap between the line and the second dot is measured. The capability of the semiconductor system is determined based on the vertical Gap. The invention further provides a chip.Type: ApplicationFiled: October 7, 2014Publication date: April 7, 2016Inventors: Wei-Chi Lee, Yu-Lin Wang, Chun-Chieh Chang, Tzu-Feng Chang, Po-Peng Lin
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Publication number: 20150348850Abstract: A mask set includes a first mask and a second mask. The first mask includes geometric patterns. The second mask includes at least a strip-shaped pattern with a first edge and a second edge opposite to the first edge. The strip-shaped pattern has a centerline along a long axis of the strip-shaped pattern. The first edge includes inwardly displaced segments shifting towards the centerline and each of the inwardly displaced segments overlaps each of the geometric patterns.Type: ApplicationFiled: May 29, 2014Publication date: December 3, 2015Applicant: UNITED MICROELECTRONICS CORP.Inventors: Wei-Chi Lee, Yu-Lin Wang, Chung-Yuan Lee
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Patent number: 8829487Abstract: A light emitting diode (LED) is provided. The LED includes a carrying substrate, a semiconductor composite layer and an electrode. The semiconductor composite layer is disposed on the carrying substrate, and an upper surface of the semiconductor composite layer includes a patterned surface and a flat surface. The electrode is disposed on the flat surface. A method for manufacturing the light emitting diode is provided as well.Type: GrantFiled: March 20, 2012Date of Patent: September 9, 2014Assignee: Walsin Lihwa CorporationInventors: Wei-Chi Lee, Shiue-Lung Chen, Jang-Ho Chen
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Patent number: 8551869Abstract: A method for roughening an epitaxy structure layer, including: providing an epitaxy structure layer; and etching a surface of the epitaxy structure layer by an excimer laser having an energy density of 1000 mJ/cm2 or less to form a roughened surface. In addition, a method for manufacturing a light-emitting diode having a roughened surface is provided.Type: GrantFiled: June 21, 2011Date of Patent: October 8, 2013Assignee: National Cheng Kung UniversityInventors: Shui-Jinn Wang, Wei-Chi Lee
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Publication number: 20120241718Abstract: A vertical light emitting diodes (LEDs) with new construction for reducing the current crowding effect and increasing the light extraction efficiency (LEE) of the LEDs is provided. By providing at least one current blocking portion corresponded to an electrode, the current flows from the electrode may be diffused or distributed more laterally instead of straight downward directly under the electrode and the current crowding effect could be reduced thereby. By providing at least one current blocking portion covered by a mirror layer to form an omni-directional reflective (ODR) structure, the internal light of the LEDs may be reflected by the ODR structure and the LEE could be increased thereby.Type: ApplicationFiled: February 16, 2012Publication date: September 27, 2012Applicant: WALSIN LIHWA CORPORATIONInventors: Shiue-Lung Chen, Wei-Chi Lee, Chang-Ho Chen
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Publication number: 20120241719Abstract: A light emitting diode (LED) is provided. The LED includes a carrying substrate, a semiconductor composite layer and an electrode. The semiconductor composite layer is disposed on the carrying substrate, and an upper surface of the semiconductor composite layer includes a patterned surface and a flat surface. The electrode is disposed on the flat surface. A method for manufacturing the light emitting diode is provided as well.Type: ApplicationFiled: March 20, 2012Publication date: September 27, 2012Applicant: WALSIN LIHWA CORPORATIONInventors: Wei-Chi Lee, Shiue-Lung Chen, Jang-Ho Chen