Abstract: An optical element driving mechanism is provided and includes a fixed assembly, a movable assembly, a driving assembly and a stopping assembly. The fixed assembly has a main axis. The movable assembly is configured to connect an optical element, and the movable assembly is movable relative to the fixed assembly. The driving assembly is configured to drive the movable assembly to move relative to the fixed assembly. The stopping assembly is configured to limit the movement of the movable assembly relative to the fixed assembly within a range of motion.

Abstract: A transceiver includes: a radio-frequency (RF) front-end circuit; a dedicated RF front-end circuit; and a switchable matching circuit, integrated in a chip. The RF front-end circuit deals with communications of a first wireless standard, and the dedicated RF front-end circuit deals with communications of a second wireless standard. The switchable matching circuit provides impedance matching between the signal port and the RF front-end circuit when the RF front-end circuit is in operation, and provides impedance matching between the signal port and the dedicated RF front-end circuit when the dedicated RF front-end circuit is in operation, and includes: a first capacitive circuit coupled to the signal port; a first switch circuit coupled between the first capacitive circuit and the dedicated RF front-end circuit; a second capacitive circuit coupled to the dedicated RF front-end circuit; and a second switch circuit coupled to a second terminal of the second capacitive circuit.

Abstract: A transceiver includes: a radio-frequency (RF) front-end circuit; a dedicated RF front-end circuit; and a switchable matching circuit, integrated in a chip. The RF front-end circuit deals with communications of a first wireless standard, and the dedicated RF front-end circuit deals with communications of a second wireless standard. The switchable matching circuit provides impedance matching between the signal port and the RF front-end circuit when the RF front-end circuit is in operation, and provides impedance matching between the signal port and the dedicated RF front-end circuit when the dedicated RF front-end circuit is in operation, and includes: a first capacitive circuit coupled to the signal port; a first switch circuit coupled between the first capacitive circuit and the dedicated RF front-end circuit; a second capacitive circuit coupled to the dedicated RF front-end circuit; and a second switch circuit coupled to a second terminal of the second capacitive circuit.

Abstract: A transceiver includes a radio-frequency (RF) front-end circuit, a dedicated RF front-end circuit, and a switchable matching circuit. The RF front-end circuit deals with communications of at least a first wireless communication standard. The dedicated RF front-end circuit deals with communications of a second wireless communication standard only. The switchable matching circuit is coupled to the RF front-end circuit, the dedicated RF front-end circuit, and a signal port of a chip. The switchable matching circuit provides impedance matching between the signal port and the RF front-end circuit when the RF front-end circuit is in operation, and provides impedance matching between the signal port and the dedicated RF front-end circuit when the dedicated RF front-end circuit is in operation. The RF front-end circuit, the dedicated RF front-end circuit, and the switchable matching circuit are integrated in the chip.

Abstract: A transceiver includes a radio-frequency (RF) front-end circuit, a dedicated RF front-end circuit, and a switchable matching circuit. The RF front-end circuit deals with communications of at least a first wireless communication standard. The dedicated RF front-end circuit deals with communications of a second wireless communication standard only. The switchable matching circuit is coupled to the RF front-end circuit, the dedicated RF front-end circuit, and a signal port of a chip. The switchable matching circuit provides impedance matching between the signal port and the RF front-end circuit when the RF front-end circuit is in operation, and provides impedance matching between the signal port and the dedicated RF front-end circuit when the dedicated RF front-end circuit is in operation. The RF front-end circuit, the dedicated RF front-end circuit, and the switchable matching circuit are integrated in the chip.

Abstract: A transceiver includes a power amplifying circuit, a first balance-unbalance circuit, a switchable matching circuit, and a low-noise amplifying circuit. The power amplifying circuit generates differential output signals during a transmitting mode of the transceiver. The first balance-unbalance circuit converts the differential output signals into a single-ended output signal. The switchable matching circuit receives the single-ended output signal on a signal port of the transceiver during the transmitting mode, and converts a single-ended receiving signal on the signal port into a single-ended input signal during a receiving mode of the transceiver. The low-noise amplifying circuit converts the single-ended input signal into a low-noise input signal during the receiving mode.

Abstract: A transceiver includes a power amplifying circuit, a first balance-unbalance circuit, a switchable matching circuit, and a low-noise amplifying circuit. The power amplifying circuit generates differential output signals during a transmitting mode of the transceiver. The first balance-unbalance circuit converts the differential output signals into a single-ended output signal. The switchable matching circuit receives the single-ended output signal on a signal port of the transceiver during the transmitting mode, and converts a single-ended receiving signal on the signal port into a single-ended input signal during a receiving mode of the transceiver. The low-noise amplifying circuit converts the single-ended input signal into a low-noise input signal during the receiving mode.

Abstract: A transceiver includes: a power amplifying circuit arranged to generate differential output signals during a transmitting mode of the transceiver; a balance-unbalance circuit arranged to convert the differential output signals into a single-ended output signal; a switchable matching circuit arranged to receive the single-ended output signal on a signal port of the transceiver during the transmitting mode, and to convert a single-ended receiving signal on the signal port into a single-ended input signal during a receiving mode of the transceiver; and a low-noise amplifying circuit arranged to convert the single-ended input signal into a low-noise input signal during the receiving mode. The power amplifying circuit, the Balun, the switchable matching circuit, and the low-noise amplifying circuit are configured as a single chip.

Abstract: A transceiver includes: a power amplifying circuit arranged to generate differential output signals during a transmitting mode of the transceiver; a balance-unbalance circuit arranged to convert the differential output signals into a single-ended output signal; a switchable matching circuit arranged to receive the single-ended output signal on a signal port of the transceiver during the transmitting mode, and to convert a single-ended receiving signal on the signal port into a single-ended input signal during a receiving mode of the transceiver; and a low-noise amplifying circuit arranged to convert the single-ended input signal into a low-noise input signal during the receiving mode. The power amplifying circuit, the Balun, the switchable matching circuit, and the low-noise amplifying circuit are configured as a single chip.

Abstract: A highly linear variable-gain low noise amplifier is a cascode amplifier. The cascode amplifier includes a gain control circuit, a load circuit, a current steering circuit and an input circuit. The gain control circuit is used for receiving a gain adjusting voltage, thereby generating a resistance adjusting signal and a current steering control signal. The load circuit includes plural variable resistors. The resistances of the variable resistors are adjusted according to the resistance adjusting signal. The current steering circuit is connected to the load circuit through plural current paths for adjusting a current ratio between the plural current paths according to the current steering control signal. The current steering circuit has differential signal output terminals. The input circuit is connected to the current steering circuit. The input circuit has differential signal input terminals.

Abstract: A highly linear variable-gain low noise amplifier is a cascode amplifier. The cascode amplifier includes a gain control circuit, a load circuit, a current steering circuit and an input circuit. The gain control circuit is used for receiving a gain adjusting voltage, thereby generating a resistance adjusting signal and a current steering control signal. The load circuit includes plural variable resistors. The resistances of the variable resistors are adjusted according to the resistance adjusting signal. The current steering circuit is connected to the load circuit through plural current paths for adjusting a current ratio between the plural current paths according to the current steering control signal. The current steering circuit has differential signal output terminals. The input circuit is connected to the current steering circuit. The input circuit has differential signal input terminals.