Patents by Inventor Wei-Chiang ONG

Wei-Chiang ONG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11690221
    Abstract: A charge pump circuit includes a power switch, a first pull-low circuit, an output pull-low circuit, a first charge pump stage and an output charge pump stage. The power switch receives an enabling signal. The first pull-low circuit and the output pull-low circuit receive a pull-low signal. The first charge pump stage includes a first boost capacitor used to receive a first phase signal, a first transfer transistor, a first gate-control transistor and a first storage capacitor used to receive a second phase signal. The output charge pump stage includes an output boost capacitor used to receive a third phase signal, an output transfer transistor and an output gate-control transistor. The charge pump circuit generates voltages in an erasing operation, a program operation and a read operation according to the enabling signal, the pull-low signal, the first phase signal, the second phase signal and the third phase signal.
    Type: Grant
    Filed: August 2, 2021
    Date of Patent: June 27, 2023
    Assignee: eMemory Technology Inc.
    Inventors: Wei-Chiang Ong, Tsung-Ta Hsieh, Chih-Yang Huang
  • Publication number: 20220052605
    Abstract: A charge pump circuit includes a power switch, a first pull-low circuit, an output pull-low circuit, a first charge pump stage and an output charge pump stage. The power switch receives an enabling signal. The first pull-low circuit and the output pull-low circuit receive a pull-low signal. The first charge pump stage includes a first boost capacitor used to receive a first phase signal, a first transfer transistor, a first gate-control transistor and a first storage capacitor used to receive a second phase signal. The output charge pump stage includes an output boost capacitor used to receive a third phase signal, an output transfer transistor and an output gate-control transistor. The charge pump circuit generates voltages in an erasing operation, a program operation and a read operation according to the enabling signal, the pull-low signal, the first phase signal, the second phase signal and the third phase signal.
    Type: Application
    Filed: August 2, 2021
    Publication date: February 17, 2022
    Applicant: eMemory Technology Inc.
    Inventors: Wei-Chiang Ong, Tsung-Ta Hsieh, Chih-Yang Huang
  • Patent number: 10734083
    Abstract: A voltage driver includes a voltage divider, a first transistor and a second transistor. The voltage divider is connected with a first voltage source and a second voltage source, and generates a first bias voltage. A drain terminal of the first transistor is connected with a third voltage source. A gate terminal of the first transistor is connected with the voltage divider to receive the first bias voltage. A drain terminal of the second transistor is connected with a source terminal of the first transistor. A gate terminal of the second transistor receives a second bias voltage. A source terminal of the second transistor is connected with a fourth voltage source. The first transistor and the second transistor are of the same conductivity type and match each other. The source terminal of the first transistor generates an output voltage.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: August 4, 2020
    Assignee: EMEMORY TECHNOLOGY INC.
    Inventors: Yu Wu, Wei-Chiang Ong, Chih-Yang Huang
  • Patent number: 10693369
    Abstract: A voltage control device includes a first charge pump, a first power switch, a second charge pump, a second power switch, and a third power switch. The first charge pump generates a first application voltage according to the first system voltage. The first power switch has a first input terminal for receiving the first system voltage, a second input terminal for receiving the first application voltage, and an output terminal. The second charge pump generates a second application voltage according to a voltage received by the input terminal of the second charge pump. The second power switch has an input terminal for receiving the second application voltage, and an output terminal. The third power switch has a first input terminal coupled to the output terminal of the first charge pump, a second input terminal coupled to the output terminal of the second charge pump, and an output terminal.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: June 23, 2020
    Assignee: eMemory Technology Inc.
    Inventors: Wei-Ming Ku, Wei-Chiang Ong
  • Publication number: 20190372456
    Abstract: A voltage control device includes a first charge pump, a first power switch, a second charge pump, a second power switch, and a third power switch. The first charge pump generates a first application voltage according to the first system voltage. The first power switch has a first input terminal for receiving the first system voltage, a second input terminal for receiving the first application voltage, and an output terminal. The second charge pump generates a second application voltage according to a voltage received by the input terminal of the second charge pump. The second power switch has an input terminal for receiving the second application voltage, and an output terminal. The third power switch has a first input terminal coupled to the output terminal of the first charge pump, a second input terminal coupled to the output terminal of the second charge pump, and an output terminal.
    Type: Application
    Filed: March 26, 2019
    Publication date: December 5, 2019
    Inventors: Wei-Ming Ku, Wei-Chiang Ong
  • Publication number: 20190115086
    Abstract: A voltage driver includes a voltage divider, a first transistor and a second transistor. The voltage divider is connected with a first voltage source and a second voltage source, and generates a first bias voltage. A drain terminal of the first transistor is connected with a third voltage source. A gate terminal of the first transistor is connected with the voltage divider to receive the first bias voltage. A drain terminal of the second transistor is connected with a source terminal of the first transistor. A gate terminal of the second transistor receives a second bias voltage. A source terminal of the second transistor is connected with a fourth voltage source. The first transistor and the second transistor are of the same conductivity type and match each other. The source terminal of the first transistor generates an output voltage.
    Type: Application
    Filed: August 27, 2018
    Publication date: April 18, 2019
    Inventors: Yu WU, Wei-Chiang ONG, Chih-Yang HUANG