Patents by Inventor Wei-Chiao Wang

Wei-Chiao Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240169167
    Abstract: The present disclosure provides a method for anti-tampering apparatus servicing data implemented by a calculation device connected to a target device, the method comprising: identifying a contract identification code and obtaining a contract package file and a contract authentication code from at least one remote device; obtaining a microservice file corresponding to the target device from the remote device when a device embedded code of the calculation device is matching the contract authentication code; performing the microservice file to enable the target device according to the contract package file and generate an execution report; publishing the execution report to the remote device to obtain an acceptance certification code; and combining and hashing the device embedded code, the contract authentication code and the acceptance certification code to generate a hash value, and sending the hash value to a blockchain.
    Type: Application
    Filed: December 22, 2022
    Publication date: May 23, 2024
    Inventors: Min-Hao LI, Yu-Chiao WANG, Ya-Ping LEE, Wei-Der CHUNG, Jhy-Ping WU
  • Patent number: 11869846
    Abstract: An interposer routing structure includes a first trace layer, a bump layer, a second trace layer and a third trace layer. The first trace layer is configured to receive a power. The bump layer is coupled to a die. The second trace layer and the third trace layer are coupled between the first trace layer and the bump layer, and include multiple ground traces and multiple power traces. The ground traces are located on both sides of at least one of the power traces, so that the ground traces isolate the at least one power trace and multiple signal traces. The power traces of the second trace layer are coupled to each other by a connecting power trace, and the ground traces of the third trace layer are coupled to each other by a connecting ground trace.
    Type: Grant
    Filed: May 5, 2023
    Date of Patent: January 9, 2024
    Assignees: GLOBAL UNICHIP CORPORATION, TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Sheng-Fan Yang, Hao-Yu Tung, Hung-Yi Chang, Wei-Chiao Wang, Yi-Tzeng Lin
  • Patent number: 11869845
    Abstract: A semiconductor wiring substrate includes a first circuit layer, a second circuit layer and a first dielectric layer. The first circuit layer includes a plurality of first signal traces and a plurality of first ground traces, wherein the first signal traces and the first ground traces are alternatively arranged on the first circuit layer, and one of the first signal traces is spaced at a first spacing from adjacent one of the first ground traces. The first dielectric layer is between the first circuit layer and the second circuit layer and has a first thickness in an arrangement direction of the first circuit layer, the first dielectric layer and the second circuit layer, wherein the first spacing substantially ranges from 0.78 to 1.96 times the first thickness.
    Type: Grant
    Filed: August 29, 2022
    Date of Patent: January 9, 2024
    Assignees: GLOBAL UNICHIP CORPORATION, TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Sheng-Fan Yang, Wei-Chiao Wang, Yi-Tzeng Lin
  • Publication number: 20230387030
    Abstract: A semiconductor wiring substrate includes a first circuit layer, a second circuit layer and a first dielectric layer. The first circuit layer includes a plurality of first signal traces and a plurality of first ground traces, wherein the first signal traces and the first ground traces are alternatively arranged on the first circuit layer, and one of the first signal traces is spaced at a first spacing from adjacent one of the first ground traces. The first dielectric layer is between the first circuit layer and the second circuit layer and has a first thickness in an arrangement direction of the first circuit layer, the first dielectric layer and the second circuit layer, wherein the first spacing substantially ranges from 0.78 to 1.96 times the first thickness.
    Type: Application
    Filed: August 29, 2022
    Publication date: November 30, 2023
    Inventors: Sheng-Fan YANG, Wei-Chiao WANG, Yi-Tzeng LIN