Patents by Inventor Wei-Chih Chien
Wei-Chih Chien has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140203235Abstract: A conductive bridge resistive memory device is provided, comprising a first electrode, a memory layer electrically coupled to the first electrode, an ion-supplying layer containing a source of ions of a first metal element capable of diffusion into and out of the memory layer, a semiconductor layer disposed between the memory layer and the ion-supplying layer, and a second electrode electrically coupled to the ion-supplying layer.Type: ApplicationFiled: April 26, 2013Publication date: July 24, 2014Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Feng-Min Lee, Yu-Yu Lin, Wei-Chih Chien, Wei-Chen Chen, Ming-Hsiu Lee
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Patent number: 8772106Abstract: Memory devices are described along with methods for manufacturing and methods for operating. A memory device as described herein includes a plurality of memory cells located between word lines and bit lines. Memory cells in the plurality of memory cells comprise a diode and a metal-oxide memory element programmable to a plurality of resistance states including a first and a second resistance state, the diode of the memory element arranged in electrical series along a current path between a corresponding word line and a corresponding bit line. The device further includes bias circuitry to apply bias arrangements across the series arrangement of the diode and the memory element of a selected memory cell in the plurality of memory cells.Type: GrantFiled: July 9, 2013Date of Patent: July 8, 2014Assignee: Macronix International Co., Ltd.Inventors: Ming-Daou Lee, Erh-Kun Lai, Kuang-Yeu Hsieh, Wei-Chih Chien, Chien Hung Yeh
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Patent number: 8699258Abstract: Memory devices and methods for operating such devices are described which can effectively program the metal-oxide memory elements in an array, while also avoiding applying unnecessarily high voltage pulses. Programming operations described herein include applying a lower voltage pulse across a metal-oxide memory element to establish a desired resistance state, and only applying a higher voltage pulse when the lower voltage pulse is insufficient to program the memory element. In doing so, issues associated with applying unnecessarily high voltages across the memory element can be avoided.Type: GrantFiled: August 18, 2011Date of Patent: April 15, 2014Assignee: Macronix International Co., Ltd.Inventors: Wei-Chih Chien, Ming-Hsiu Lee, Yan-Ru Chen
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Publication number: 20140027706Abstract: A switching device and an operating method for the same and a memory array are provided. The switching device comprises a first solid electrolyte, a second solid electrolyte and a switching layer. The switching layer is adjoined between the first solid electrolyte and the second solid electrolyte.Type: ApplicationFiled: July 30, 2012Publication date: January 30, 2014Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Wei-Chih Chien, Feng-Ming Lee, Ming-Hsiu Lee
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Publication number: 20130343115Abstract: A resistance memory cell is provided and includes a first electrode, a tungsten metal layer, a metal oxide layer, and a second electrode. The tungsten metal layer is disposed on the first electrode. The metal oxide layer is disposed on the tungsten metal layer. The second electrode includes a first connection pad, a second connection pad, and a bridge portion electrically connected between the first connection pad and the second connection pad. The bridge portion is disposed on the metal oxide layer or surrounds the metal oxide layer. The resistance memory cell adjusts a resistivity of the metal oxide layer through a first current path, passing through the metal oxide layer and the tungsten metal layer, or a second current path extending from the first connection pad to the second connection pad.Type: ApplicationFiled: August 31, 2012Publication date: December 26, 2013Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: WEI-CHIH CHIEN, MING-HSIU LEE
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Publication number: 20130341583Abstract: A resistive memory and a fabricating method thereof are provided. The resistive memory includes first and second electrodes, a variable resistance material layer, a first dielectric layer, and a second dielectric layer. The first electrode includes a first portion and a second portion. The second electrode is disposed opposite to the first electrode. The variable resistance material layer includes a sidewall and first and second surfaces opposite to each other, wherein the first surface is connected with the first portion of the first electrode and the second surface is electrically connected with the second electrode. The second portion surrounds the sidewall of the variable resistance material layer and is connected with the first portion. The first dielectric layer is disposed between the first and the second electrodes. The second dielectric layer is disposed between the variable resistance material layer and the second portion of the first electrode.Type: ApplicationFiled: March 22, 2013Publication date: December 26, 2013Applicant: MACRONIX International Co., Ltd.Inventors: Ming-Hsiu Lee, Wei-Chih Chien
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Publication number: 20130341753Abstract: A disclosed memory device includes a three-dimension array structure that includes memory layers and transistor structures disposed between the memory layers. Each memory layer is connected to a common electrode, and each transistor structure includes transistors that share common column structures and common base structures. The transistors also each include a connector structure that is spaced apart from a common column structure by a common base structure.Type: ApplicationFiled: June 20, 2012Publication date: December 26, 2013Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Ming-Hsiu LEE, Wei-Chih CHIEN
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Publication number: 20130295719Abstract: Memory devices are described along with methods for manufacturing and methods for operating. A memory device as described herein includes a plurality of memory cells located between word lines and bit lines. Memory cells in the plurality of memory cells comprise a diode and a metal-oxide memory element programmable to a plurality of resistance states including a first and a second resistance state, the diode of the memory element arranged in electrical series along a current path between a corresponding word line and a corresponding bit line. The device further includes bias circuitry to apply bias arrangements across the series arrangement of the diode and the memory element of a selected memory cell in the plurality of memory cells.Type: ApplicationFiled: July 9, 2013Publication date: November 7, 2013Inventors: Ming-Daou Lee, Erh-Kun Lai, Kuang-Yeu Hsieh, Wei-Chih Chien, Chien Hung Yeh
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Patent number: 8488362Abstract: Memory devices are described along with methods for manufacturing and methods for operating. A memory device as described herein includes a plurality of memory cells located between word lines and bit lines. Memory cells in the plurality of memory cells comprise a diode and a metal-oxide memory element programmable to a plurality of resistance states including a first and a second resistance state, the diode of the memory element arranged in electrical series along a current path between a corresponding word line and a corresponding bit line. The device further includes bias circuitry to apply bias arrangements across the series arrangement of the diode and the memory element of a selected memory cell in the plurality of memory cells.Type: GrantFiled: April 29, 2009Date of Patent: July 16, 2013Assignee: Macronix International Co., Ltd.Inventors: Ming-Daou Lee, Erh-Kun Lai, Kuang-Yeu Hsieh, Wei-Chih Chien, Chien-Hung Yeh
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Publication number: 20130153846Abstract: A self-aligning stacked memory cell array structure and method for fabricating such structure. The memory cell array includes a stack of memory cells disposed adjacent to opposing sides of a conductive line that is formed within a trench. The memory cells are stacked such that the memory element surface of each memory cell forms a portion of the sidewall of the conductive line. The conductive line is formed within the trench such that electrical contact is made across the entire memory element surface of each memory cell. Such structure and method for making such structure is a self-aligning process that does not require the use of any additional masks.Type: ApplicationFiled: December 19, 2011Publication date: June 20, 2013Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Wei-Chih CHIEN, Ming-Hsiu Lee, Shih-Hung Chen
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Publication number: 20130094273Abstract: A 3D memory device is based on an array of conductive pillars and a plurality of patterned conductor planes including left side and right side conductors adjacent the conductive pillars at left side and right side interface regions. Memory elements in the left side and right side interface regions comprise a programmable transition metal oxide which can be characterized by built-in self-switching behavior, or other programmable resistance material. The conductive pillars can be selected using two-dimensional decoding, and the left side and right side conductors in the plurality of planes can be selected using decoding on a third dimension, combined with left and right side selection.Type: ApplicationFiled: December 5, 2012Publication date: April 18, 2013Inventors: WEI-CHIH CHIEN, MING-HSIU LEE, HSIANG-LAN LUNG
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Patent number: 8331127Abstract: A memory device comprises an array of memory cells each capable of storing multiple bits of data. The memory cells are arranged in memory strings that are connected to a common source line. Each memory cell includes a programmable transistor connected in parallel with a resistance switching device. The transistor is switchable between a plurality of different threshold voltages associated with respective memory states. The resistance switching device is configured to be switchable between a plurality of different resistances associated with respective memory states.Type: GrantFiled: May 24, 2010Date of Patent: December 11, 2012Assignee: Macronix International Co., Ltd.Inventors: Yi-Chou Chen, Wei-Chih Chien, Feng-Ming Lee
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Patent number: 8295075Abstract: A resistive memory and a method for controlling operations of the resistive memory are provided. The resistive memory has a first memory layer, a second memory layer and a medium layer. Each of the first memory layer and the second memory layer is used to store data. The medium layer is formed between the first memory layer and the second memory layer. The method comprises at least a step of measuring a resistance between the first memory layer and the second memory layer, and determining which one of a first state, a second state and a third state is a state of the resistive memory according to the measured resistance.Type: GrantFiled: April 2, 2010Date of Patent: October 23, 2012Assignee: MACRONIX International Co., Ltd.Inventors: Wei-Chih Chien, Yi-Chou Chen, Feng-Ming Lee
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Patent number: 8279656Abstract: A memory cell is arranged to enhance the electrical field of the memory element. The memory cell has a metal-oxide memory element, a nonconductive element, and a conductive element. The metal-oxide memory element is in a current path between a first electrode at a first voltage and a second electrode at a second voltage. The nonconductive element is adjacent to the metal-oxide memory element.Type: GrantFiled: December 10, 2010Date of Patent: October 2, 2012Assignee: Macronix International Co., Ltd.Inventors: Wei-Chih Chien, Yan-Ru Chen, Yi-Chou Chen
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Publication number: 20120188813Abstract: Memory devices and methods for operating such devices are described which can effectively program the metal-oxide memory elements in an array, while also avoiding applying unnecessarily high voltage pulses. Programming operations described herein include applying a lower voltage pulse across a metal-oxide memory element to establish a desired resistance state, and only applying a higher voltage pulse when the lower voltage pulse is insufficient to program the memory element. In doing so, issues associated with applying unnecessarily high voltages across the memory element can be avoided.Type: ApplicationFiled: August 18, 2011Publication date: July 26, 2012Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Wei-Chih Chien, Ming-Hsiu Lee, Yan-Ru Chen
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Patent number: 8149610Abstract: A memory device comprises an array of memory cells each capable of storing multiple bits of data. Each memory cell includes a programmable transistor in series with a resistance switching device. The transistor is switchable between a plurality of different threshold voltages associated with respective memory states. The resistance switching device is configured to be switchable between a plurality of different resistances associated with respective memory states.Type: GrantFiled: May 12, 2010Date of Patent: April 3, 2012Assignee: Macronix International Co., Ltd.Inventors: Yi-Chou Chen, Wei-Chih Chien, Feng-Ming Lee
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Patent number: 8134865Abstract: Metal-oxide based memory devices and methods for operating and manufacturing such devices are described herein. A method for manufacturing a memory device as described herein comprises forming a metal-oxide memory element, and applying an activating energy to the metal-oxide memory element. In embodiments the activating energy can be applied by applying electrical and/or thermal energy to the metal-oxide material.Type: GrantFiled: February 6, 2009Date of Patent: March 13, 2012Assignee: Macronix International Co., Ltd.Inventors: Kuo-Pin Chang, Yi-Chou Chen, Wei-Chih Chien, Erh-Kun Lai
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Publication number: 20110317471Abstract: A memory cell is arranged to enhance the electrical field of the memory element. The memory cell has a metal-oxide memory element, a nonconductive element, and a conductive element. The metal-oxide memory element is in a current path between a first electrode at a first voltage and a second electrode at a second voltage. The nonconductive element is adjacent to the metal-oxide memory element.Type: ApplicationFiled: December 10, 2010Publication date: December 29, 2011Applicant: Macronix International Co., Ltd.Inventors: Wei-Chih Chien, Yan-Ru Chen, Yi-Chou Chen
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Patent number: 8067815Abstract: Memory devices are described along with methods for manufacturing. A memory device as described herein includes a first electrode and a second electrode. The memory device further includes a diode and an anti-fuse metal-oxide memory element comprising aluminum oxide and copper oxide. The diode and the metal-oxide memory element are arranged in electrical series between the first electrode and the second electrode.Type: GrantFiled: December 11, 2008Date of Patent: November 29, 2011Assignee: Macronix International Co., Lt.d.Inventors: Wei-Chih Chien, Kuo-Pin Chang, Yi-Chou Chen, Erh-Kun Lai, Kuang-Yeu Hsieh
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Publication number: 20110286258Abstract: A memory device comprises an array of memory cells each capable of storing multiple bits of data. The memory cells are arranged in memory strings that are connected to a common source line. Each memory cell includes a programmable transistor connected in parallel with a resistance switching device. The transistor is switchable between a plurality of different threshold voltages associated with respective memory states. The resistance switching device is configured to be switchable between a plurality of different resistances associated with respective memory states.Type: ApplicationFiled: May 24, 2010Publication date: November 24, 2011Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Yi-Chou Chen, Wei-Chih Chien, Feng-Ming Lee