Patents by Inventor Wei-Chih Hsieh
Wei-Chih Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240143880Abstract: A method includes determining a first timing of a transition sequence of a signal on a first path of an integrated circuit (IC) design, the first timing being based on an IC design signoff voltage, determining a second timing of the transition sequence of the signal on the first path, the second timing being based on the signoff voltage and a first voltage drop along the first path, calculating a first path derating factor based on a timing gap between the first and second timings of the transition sequence, and using the first path derating factor to evaluate the IC design.Type: ApplicationFiled: January 27, 2023Publication date: May 2, 2024Inventors: Yu-Wen LIN, Bogdan TUTUIANU, Florentin DARTU, Wei-Chih HSIEH, Osamu TAKAHASHI
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Publication number: 20240139301Abstract: The disclosure provides a method of active immunotherapy for a cancer patient, comprising administering vaccines against Globo series antigens (i.e., Globo H, SSEA-3 and SSEA-4). Specifically, the method comprises administering Globo H-CRM197 (OBI-833/821) in patients with cancer. The disclosure also provides a method of selecting a cancer patient who is suitable as treatment candidate for immunotherapy. Exemplary immune response can be characterized by reduction of the severity of disease, including but not limited to, prevention of disease, delay in onset of disease, decreased severity of symptoms, decreased morbidity and delayed mortality.Type: ApplicationFiled: November 19, 2021Publication date: May 2, 2024Inventors: Ming-Tain LAI, Cheng-Der Tony YU, I-Ju CHEN, Wei-Han LEE, Chueh-Hao YANG, Chun-Yen TSAO, Chang-Lin HSIEH, Chien-Chih OU, Chen-En TSAI
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Publication number: 20230385512Abstract: A method (of manufacturing a semiconductor device, a corresponding layout diagram being stored on a non-transitory computer-readable medium, the layout diagram including a subset of transistor-to-well-edge-influenced (TWEI) cells, each TWEI cell including one or more transistors in one or more corresponding wells) includes generating a netlist which represents the subset, the generating a netlist including: In some embodiments, for each TWEI cell represented in the netlist, and for a given transistor in a given well in a given cell, expanding the netlist to include one or more proximity-effect-inducer (PEI) parameters, each PEI parameter being related to an intra-cell physical proximity of the given transistor to an edge of the given well (given well-edge).Type: ApplicationFiled: August 10, 2023Publication date: November 30, 2023Inventors: Yen-Pin CHEN, Florentin DARTU, Wei-Chih HSIEH, Tzu-Hen LIN, Chung-Hsing WANG
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Publication number: 20220245318Abstract: For a method of manufacturing a semiconductor device, a corresponding layout diagram is stored on a non-transitory computer-readable medium, the layout diagram being arranged relative to first and second perpendicular directions, the layout diagram including cells such that, for a subset of the cells, each subject one of the cells (subject cell) in the subset has a neighborhood including first and second neighbor cells on corresponding first and second sides of the subject cell relative to the first direction. The method includes: for each subject cell in the subset, generating a sidefile which represents neighborhood-specific proximity-effect information.Type: ApplicationFiled: June 22, 2021Publication date: August 4, 2022Inventors: Yen-Pin CHEN, Florentin DARTU, Wei-Chih HSIEH, Tzu-Hen LIN, Chung-Hsing WANG
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Patent number: 11387818Abstract: A device is disclosed and includes a first transistor, a second transistor, and a first current limiter. First terminals of the first and second transistors are coupled to an output terminal, and gate terminals of the first and second transistors receive a first input signal. A first terminal of the first current limiter is coupled to a second terminal of the first transistor to output a first output signal, and a second terminal of the first current limiter is coupled to a second terminal of the second transistor to output a second output signal. A third output signal at the output terminal has a logic value different from that of the first input signal.Type: GrantFiled: July 12, 2021Date of Patent: July 12, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yu-Lun Ou, Wei-Chih Hsieh, Shang-Chih Hsieh
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Publication number: 20210344330Abstract: A device is disclosed and includes a first transistor, a second transistor, and a first current limiter. First terminals of the first and second transistors are coupled to an output terminal, and gate terminals of the first and second transistors receive a first input signal. A first terminal of the first current limiter is coupled to a second terminal of the first transistor to output a first output signal, and a second terminal of the first current limiter is coupled to a second terminal of the second transistor to output a second output signal. A third output signal at the output terminal has a logic value different from that of the first input signal.Type: ApplicationFiled: July 12, 2021Publication date: November 4, 2021Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yu-Lun OU, Wei-Chih HSIEH, Shang-Chih HSIEH
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Patent number: 11063578Abstract: A device is disclosed and includes a first switch, a second switch, and a selector. The first switch outputs a first output signal at a first terminal thereof. The second switch is coupled to the first switch at a second terminal of the first switch. The second switch outputs a second output signal at the second terminal of the first switch in response to an input signal. The selector outputs, in response to the input signal received at two terminal of the selector, one of the first and second output signals as a third output signal. The third output signal has a logic value different from the input signal.Type: GrantFiled: August 27, 2020Date of Patent: July 13, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yu-Lun Ou, Wei-Chih Hsieh, Shang-Chih Hsieh
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Publication number: 20200395924Abstract: A device is disclosed and includes a first switch, a second switch, and a selector. The first switch outputs a first output signal at a first terminal thereof. The second switch is coupled to the first switch at a second terminal of the first switch. The second switch outputs a second output signal at the second terminal of the first switch in response to an input signal. The selector outputs, in response to the input signal received at two terminal of the selector, one of the first and second output signals as a third output signal. The third output signal has a logic value different from the input signal.Type: ApplicationFiled: August 27, 2020Publication date: December 17, 2020Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yu-Lun OU, Wei-Chih HSIEH, Shang-Chih HSIEH
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Patent number: 10778197Abstract: A device is disclosed that includes a level shifter and an output stage. The level shifter is configured to generate a first output signal based on a logic value of a first input signal. The output stage is configured to receive the first output signal transmitted according to the logic value of the first input signal, and to generate a second output signal. The second output signal has a logic value that is different from a logic value of the first output signal, and the second output signal and the first input signal has a same logic value.Type: GrantFiled: November 16, 2019Date of Patent: September 15, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yu-Lun Ou, Wei-Chih Hsieh, Shang-Chih Hsieh
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Publication number: 20200083871Abstract: A device is disclosed that includes a level shifter and an output stage. The level shifter is configured to generate a first output signal based on a logic value of a first input signal. The output stage is configured to receive the first output signal transmitted according to the logic value of the first input signal, and to generate a second output signal. The second output signal has a logic value that is different from a logic value of the first output signal, and the second output signal and the first input signal has a same logic value.Type: ApplicationFiled: November 16, 2019Publication date: March 12, 2020Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yu-Lun OU, Wei-Chih HSIEH, Shang-Chih HSIEH
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Patent number: 10483950Abstract: A device is disclosed that includes a level shifter and an output stage. The level shifter is configured to output a first output signal at a first output terminal in response to a first input signal having a first logic level, and is configured to output a second output signal at a second output terminal in response to the first input signal having a second logic level. The output stage is configured to receive and adjust the first output signal or the second output signal that is selected in response to the first input signal, and configured to generate a third output signal, wherein the third output signal has a logic value that is the same as a logic value of the first output signal or the second output signal.Type: GrantFiled: May 13, 2019Date of Patent: November 19, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yu-Lun Ou, Wei-Chih Hsieh, Shang-Chih Hsieh
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Publication number: 20190280678Abstract: A device is disclosed that includes a level shifter and an output stage. The level shifter is configured to output a first output signal at a first output terminal in response to a first input signal having a first logic level, and is configured to output a second output signal at a second output terminal in response to the first input signal having a second logic level. The output stage is configured to receive and adjust the first output signal or the second output signal that is selected in response to the first input signal, and configured to generate a third output signal, wherein the third output signal has a logic value that is the same as a logic value of the first output signal or the second output signal.Type: ApplicationFiled: May 13, 2019Publication date: September 12, 2019Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yu-Lun OU, Wei-Chih HSIEH, Shang-Chih HSIEH
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Patent number: 10291210Abstract: A device is disclosed that includes a level shifter and a selector. The level shifter is configured to output a first output signal at a first output terminal in response to a first input signal having a first logic level, and is configured to output a second output signal at a second output terminal in response to the first input signal having a second logic level. The selector is coupled to the first output terminal and the second output terminal. The selector is configured to pass one of the first output signal or the second output signal in response to the first input signal, to an output of the selector.Type: GrantFiled: December 13, 2018Date of Patent: May 14, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yu-Lun Ou, Wei-Chih Hsieh, Shang-Chih Hsieh
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Publication number: 20190115905Abstract: A device is disclosed that includes a level shifter and a selector. The level shifter is configured to output a first output signal at a first output terminal in response to a first input signal having a first logic level, and is configured to output a second output signal at a second output terminal in response to the first input signal having a second logic level. The selector is coupled to the first output terminal and the second output terminal. The selector is configured to pass one of the first output signal or the second output signal in response to the first input signal, to an output of the selector.Type: ApplicationFiled: December 13, 2018Publication date: April 18, 2019Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yu-Lun OU, Wei-Chih HSIEH, Shang-Chih HSIEH
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Patent number: 10164615Abstract: A device is disclosed that includes a level shifter and an output stage. The level shifter includes a first current limiter. The level shifter is configured to generate a first output signal at a first terminal of the first current limiter, and to generate a second output signal at a second terminal of the first current limiter according to a first input signal. The output stage is configured to adjust a voltage swing of a selected one of the first output signal and the second output signal.Type: GrantFiled: December 21, 2017Date of Patent: December 25, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yu-Lun Ou, Wei-Chih Hsieh, Shang-Chih Hsieh
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Publication number: 20180115307Abstract: A device is disclosed that includes a level shifter and an output stage. The level shifter includes a first current limiter. The level shifter is configured to generate a first output signal at a first terminal of the first current limiter, and to generate a second output signal at a second terminal of the first current limiter according to a first input signal. The output stage is configured to adjust a voltage swing of a selected one of the first output signal and the second output signal.Type: ApplicationFiled: December 21, 2017Publication date: April 26, 2018Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yu-Lun OU, Wei-Chih HSIEH, Shang-Chih HSIEH
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Patent number: 9866205Abstract: A device is disclosed that includes a level shifter and a selector. The level shifter includes a first current limiter. The level shifter is configured to generate a first output signal at a first terminal of the first current limiter, and to generate a second output signal at a second terminal of the first current limiter according to a first input signal. The selector configured to selectively transmit one of the first output signal and the second output signal according to the first input signal.Type: GrantFiled: November 16, 2015Date of Patent: January 9, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yu-Lun Ou, Wei-Chih Hsieh, Shang-Chih Hsieh
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Publication number: 20170141765Abstract: A device is disclosed that includes a level shifter and a selector. The level shifter includes a first current limiter. The level shifter is configured to generate a first output signal at a first terminal of the first current limiter, and to generate a second output signal at a second terminal of the first current limiter according to a first input signal. The selector configured to selectively transmit one of the first output signal and the second output signal according to the first input signal.Type: ApplicationFiled: November 16, 2015Publication date: May 18, 2017Inventors: Yu-Lun OU, Wei-Chih HSIEH, Shang-Chih HSIEH
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Patent number: 9142630Abstract: Among other things, one or more techniques for enhancing device (e.g., transistor) performance are provided herein. In one embodiment, device performance is enhanced by forming an extended dummy region at an edge of a region of a device and forming an active region at a non-edge of the region. Limitations associated with semiconductor fabrication processing present in the extended dummy region more so than in non-edge regions. Accordingly, a device exhibiting enhanced performance is formed by connecting a gate to the active region, where the active region has a desired profile because it is comprised within a non-edge of the region. A dummy device (e.g., that may be less responsive) may be formed to include the extended dummy region, where the extended dummy region has a less than desired profile due to limitations associated with semiconductor fabrication processing, for example.Type: GrantFiled: July 25, 2012Date of Patent: September 22, 2015Assignee: Taiwan Semiconductor Manufacturing Co. LimitedInventors: Chang-Yu Wu, Chih-Chiang Chang, Shang-Chih Hsieh, Wei-Chih Hsieh
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Publication number: 20140027821Abstract: Among other things, one or more techniques for enhancing device (e.g., transistor) performance are provided herein. In one embodiment, device performance is enhanced by forming an extended dummy region at an edge of a region of a device and forming an active region at a non-edge of the region. Limitations associated with semiconductor fabrication processing present in the extended dummy region more so than in non-edge regions. Accordingly, a device exhibiting enhanced performance is formed by connecting a gate to the active region, where the active region has a desired profile because it is comprised within a non-edge of the region. A dummy device (e.g., that may be less responsive) may be formed to include the extended dummy region, where the extended dummy region has a less than desired profile due to limitations associated with semiconductor fabrication processing, for example.Type: ApplicationFiled: July 25, 2012Publication date: January 30, 2014Applicant: Taiwan Semiconductor Manufacturing Company LimitedInventors: Chang-Yu Wu, Chih-Chiang Chang, Shang-Chih Hsieh, Wei-Chih Hsieh