Abstract: The present disclosure provides a privacy computing method based on homomorphic encryption, which includes steps as follows. The ciphertext data is received, where the ciphertext data has a floating-point homomorphic encryption data structure, and the floating-point homomorphic encryption data structure of the ciphertext data includes the ciphertext mantissa, exponent parameter and gain parameter. The gain parameter sets the precision of the floating point corresponding to the ciphertext mantissa. The exponent parameter is adapted to multiplication or division. The artificial intelligence model performs operations on the ciphertext data to return the ciphertext result.

Abstract: A layer stack including a first bonding dielectric material layer, a dielectric metal oxide layer, and a second bonding dielectric material layer is formed over a top surface of a substrate including a substrate semiconductor layer. A conductive material layer is formed by depositing a conductive material over the second bonding dielectric material layer. The substrate semiconductor layer is thinned by removing portions of the substrate semiconductor layer that are distal from the layer stack, whereby a remaining portion of the substrate semiconductor layer includes a top semiconductor layer. A semiconductor device may be formed on the top semiconductor layer.

Abstract: A semiconductor die package includes an inductor-capacitor (LC) semiconductor die that is directly bonded with a logic semiconductor die. The LC semiconductor die includes inductors and capacitors that are integrated into a single die. The inductors and capacitors of the LC semiconductor die may be electrically connected with transistors and other logic components on the logic semiconductor die to form a voltage regulator circuit of the semiconductor die package. The integration of passive components (e.g., the inductors and capacitors) of the voltage regulator circuit into a single semiconductor die reduces signal propagation distances in the voltage regulator circuit, which may increase the operating efficiency of the voltage regulator circuit, may reduce the formfactor for the semiconductor die package, may reduce parasitic capacitance and/or may reduce parasitic inductance in the voltage regulator circuit (thereby improving the performance of the voltage regulator circuit), among other examples.

Abstract: A method for determining parameters of nanostructures, wherein the method includes steps as follows: Firstly, an X-ray reflection intensity measurement curve of a nanostructure to be tested is obtained by radiating the nanostructure to be tested with X-ray. The X-ray reflection intensity measurement curve is compared with an X-ray reflection intensity standard curve to obtain a comparison result. Subsequently, at least one parameter existing in the nanostructure to be tested is determined according to the comparison result.

Abstract: This disclosure relates to an X-ray reflectometry apparatus and a method for measuring a three-dimensional nanostructure on a flat substrate. The X-ray reflectometry apparatus comprises an X-ray source, an X-ray reflector, a 2-dimensional X-ray detector, and a two-axis moving device. The X-ray source is for emitting X-ray. The X-ray reflector is configured for reflecting the X-ray onto a sample surface. The 2-dimensional X-ray detector is configured to collect a reflecting X-ray signal from the sample surface. The two-axis moving device is configured to control two-axis directions of the 2-dimensional X-ray detector to move on at least one of x-axis and z-axis with a formula concerning an incident angle of the X-ray with respect to the sample surface for collecting the reflecting X-ray signal.

Abstract: A semiconductor device according to embodiments of the present disclosure includes a first die including a first bonding layer and a second die including a second hybrid bonding layer. The first bonding layer includes a first dielectric layer and a first metal coil embedded in the first dielectric layer. The second bonding layer includes a second dielectric layer and a second metal coil embedded in the second dielectric layer. The second hybrid bonding layer is bonded to the first hybrid bonding layer such that the first dielectric layer is bonded to the second dielectric layer and the first metal coil is bonded to the second metal coil.

Abstract: The federated learning system includes a moderator and client devices. Each client device performs a method for verifying model update as follows: receiving a hash function and a general model; training a client model according to the general model and raw data; calculating a difference as an update parameter between the general model and the client model, sending the update parameter to the moderator; inputting the update parameter to the hash function to generate a hash value; sending the hash value to other client devices, and receiving other hash values; summing all the hash values to generate a trust value; receiving an aggregation parameter calculated according to the update parameters; inputting the aggregation parameter to the hash function to generate a to-be-verified value; and updating the client model according to the aggregation parameter when the to-be-verified value equals the trust value.

Abstract: A microelectronic 3D packaging structure and a method of manufacturing the same are introduced. The microelectronic 3D packaging structure includes a first board with a plurality of a first edges and disposed with a first electronic device; a second board with a plurality of a second edges and disposed with a second electronic device, wherein at least one second edge of the second board is jointed to at least one first edge of the first board to form a joint line; and a joint connection portion disposed at the joint line of the two adjacent boards and adapted to function as a connection path for transmitting signals.

Abstract: A microelectronic 3D packaging structure and a method of manufacturing the same are introduced. The microelectronic 3D packaging structure includes a first board with a plurality of a first edges and disposed with a first electronic device; a second board with a plurality of a second edges and disposed with a second electronic device, wherein at least one second edge of the second board is jointed to at least one first edge of the first board to form a joint line; and a joint connection portion disposed at the joint line of the two adjacent boards and adapted to function as a connection path for transmitting signals.