Patents by Inventor Wei-Chun Tan

Wei-Chun Tan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240178328
    Abstract: Embodiments include a Schottky barrier diode (SBD) structure and method of forming the same, the SBD structure including a current blockage feature to inhibit current from leaking at an interface with a shallow trench isolation regions surrounding an anode region of the SBD structure.
    Type: Application
    Filed: May 1, 2023
    Publication date: May 30, 2024
    Inventors: Cheng-Hsien Wu, Chien-Lin Tseng, Sheng Yu Lin, Ting-Chang Chang, Yung-Fang Tan, Yu-Fa Tu, Wei-Chun Hung
  • Patent number: 11978510
    Abstract: The present disclosure generally relates to memory devices and methods of forming the same. More particularly, the present disclosure relates to resistive random-access (ReRAM) memory devices incorporating reference cells for achieving high sensing yield. The present disclosure provides a memory device including a main cell structure including a switching element arranged between a pair of conductors, and a reference cell structure electrically coupled to the main cell structure. The reference cell structure includes a switching element arranged between a pair of conductors, in which the switching element of the reference cell structure has a dimension that is different from a dimension of the switching element of the main cell structure.
    Type: Grant
    Filed: July 28, 2021
    Date of Patent: May 7, 2024
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Curtis Chun-I Hsieh, Wei-Hui Hsu, Wanbing Yi, Yi Jiang, Kai Kang, Juan Boon Tan
  • Patent number: 11205597
    Abstract: A method includes forming a first fin extending from a substrate, forming a first gate stack over and along sidewalls of the first fin, forming a first spacer along a sidewall of the first gate stack, the first spacer including a first composition of silicon oxycarbide, forming a second spacer along a sidewall of the first spacer, the second spacer including a second composition of silicon oxycarbide, forming a third spacer along a sidewall of the second spacer, the third spacer including silicon nitride, and forming a first epitaxial source/drain region in the first fin and adjacent the third spacer.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: December 21, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Chun Tan, I-Hsieh Wong, Te-En Cheng, Yung-Hui Lin, Wei-Ken Lin, Wei-Yang Lee, Chih-Hung Nien
  • Publication number: 20200105620
    Abstract: A method includes forming a first fin extending from a substrate, forming a first gate stack over and along sidewalls of the first fin, forming a first spacer along a sidewall of the first gate stack, the first spacer including a first composition of silicon oxycarbide, forming a second spacer along a sidewall of the first spacer, the second spacer including a second composition of silicon oxycarbide, forming a third spacer along a sidewall of the second spacer, the third spacer including silicon nitride, and forming a first epitaxial source/drain region in the first fin and adjacent the third spacer.
    Type: Application
    Filed: July 1, 2019
    Publication date: April 2, 2020
    Inventors: Wei-Chun Tan, I-Hsieh Wong, Te-En Cheng, Yung-Hui Lin, Wei-Ken Lin, Wei-Yang Lee, Chih-Hung Nien