Patents by Inventor Wei Chung Wu
Wei Chung Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240170299Abstract: A method for manufacturing a semiconductor device includes: providing a wafer-bonding stack structure having a sidewall layer and an exposed first component layer; forming a photoresist layer on the first component layer; performing an edge trimming process to at least remove the sidewall layer; and removing the photoresist layer. In this way, contaminant particles generated from the blade during the edge trimming process may fall on the photoresist layer but not fall on the first component layer, so as to protect the first component layer from being contaminated.Type: ApplicationFiled: January 30, 2024Publication date: May 23, 2024Inventors: KUN-JU LI, ANG CHAN, HSIN-JUNG LIU, WEI-XIN GAO, JHIH-YUAN CHEN, CHUN-HAN CHEN, ZONG-SIAN WU, CHAU-CHUNG HOU, I-MING LAI, FU-SHOU TSAI
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Patent number: 11982798Abstract: A projection lens includes a first lens group, a second lens group and an aperture stop. The first lens group is disposed between a reduced side and a magnified side. The second lens is disposed between the first lens group and the magnified side. The second lens group has a light incident surface, a reflective surface and a light emitting surface, the light incident surface faces the first lens group, the light emitting surface faces a projection surface, the light incident surface, the light emitting surface and the first lens group are disposed at a single side of the reflective surface, and at least one of the light incident surface, the reflective surface and the light emitting surface is a freeform surface. The aperture stop is disposed between the first lens group and the second lens group. Moreover, a projection apparatus including the projection lens is also provided.Type: GrantFiled: November 5, 2021Date of Patent: May 14, 2024Assignee: Coretronic CorporationInventors: Hsin-Hsiang Lo, Wei-Ting Wu, Fu-Ming Chuang, Chuan-Chung Chang, Ching-Chuan Wei
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Publication number: 20240094094Abstract: A pump health analysis method and a pump health analysis device using the same are provided. A standard vibration curve of a standard pump is obtained. The standard vibration curve is converted from a time domain to a frequency domain to obtain a first frequency distribution curve. A sample vibration curve of a sample pump is obtained. The sample vibration curve is converted from the time domain to the frequency domain to obtain a second frequency distribution curve. The first frequency distribution curve is compared with the second frequency distribution curve by using a cosine similarity algorithm to obtain a health index of the sample pump.Type: ApplicationFiled: November 9, 2022Publication date: March 21, 2024Inventors: Wei-Chen WU, Cheng-Tai PENG, Chih-Chung KUO
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Publication number: 20240084983Abstract: The disclosure includes a convertible light device comprising a device housing, a battery pack removably coupled to the housing, and an elongate flexible light source detachably coupled to the device housing and electrically coupled to the battery pack, where the elongate flexible light source comprises a plurality of LEDs. In some embodiments, the convertible light device is configured to convert between a rope mode and a lantern mode. In the rope mode, the elongate flexible light source may be configured to extend from the device housing. In the lantern mode, the elongate flexible light source may be configured to wrap around the device housing.Type: ApplicationFiled: November 15, 2023Publication date: March 14, 2024Inventors: Arthur Chao-Chung Wu, Jarret Weis, David Burns
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Patent number: 11923205Abstract: A method for manufacturing a semiconductor device includes: providing a wafer-bonding stack structure having a sidewall layer and an exposed first component layer; forming a photoresist layer on the first component layer; performing an edge trimming process to at least remove the sidewall layer; and removing the photoresist layer. In this way, contaminant particles generated from the blade during the edge trimming process may fall on the photoresist layer but not fall on the first component layer, so as to protect the first component layer from being contaminated.Type: GrantFiled: December 17, 2021Date of Patent: March 5, 2024Assignee: UNITED MICROELECTRONICS CORPORATIONInventors: Kun-Ju Li, Ang Chan, Hsin-Jung Liu, Wei-Xin Gao, Jhih-Yuan Chen, Chun-Han Chen, Zong-Sian Wu, Chau-Chung Hou, I-Ming Lai, Fu-Shou Tsai
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Patent number: 10818653Abstract: A control circuit providing an output voltage and including an N-type transistor, a first P-type transistor and a second P-type transistor is provided. The N-type transistor is coupled to a first power terminal. The first P-type transistor includes a first source, a first drain, a first gate and a first bulk. The first gate is coupled to a gate of the N-type transistor. The first bulk is coupled to the first source. The second P-type transistor includes a second source, a second drain, a second gate and a second bulk. The second source is coupled to a second power terminal. The second drain and the second bulk are coupled to the first bulk.Type: GrantFiled: December 12, 2017Date of Patent: October 27, 2020Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATIONInventors: Shao-Chang Huang, Shang-Chuan Pai, Wei-Chung Wu, Szu-Chi Chen, Sheng-Chih Chuang, Yin-Ting Lin, Pei-Chun Yu, Han-Pei Liu, Jung-Tsun Chuang, Chieh-Yao Chuang, Hung-Wei Chen
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Publication number: 20190181135Abstract: A control circuit providing an output voltage and including an N-type transistor, a first P-type transistor and a second P-type transistor is provided. The N-type transistor is coupled to a first power terminal. The first P-type transistor includes a first source, a first drain, a first gate and a first bulk. The first gate is coupled to a gate of the N-type transistor. The first bulk is coupled to the first source. The second P-type transistor includes a second source, a second drain, a second gate and a second bulk. The second source is coupled to a second power terminal. The second drain and the second bulk are coupled to the first bulk.Type: ApplicationFiled: December 12, 2017Publication date: June 13, 2019Applicant: Vanguard International Semiconductor CorporationInventors: Shao-Chang HUANG, Shang-Chuan PAI, Wei-Chung WU, Szu-Chi CHEN, Sheng-Chih CHUANG, Yin-Ting LIN, Pei-Chun YU, Han-Pei LIU, Jung-Tsun CHUANG, Chieh-Yao CHUANG, Hung-Wei CHEN
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Publication number: 20180091127Abstract: A delay circuit is provided. The delay circuit includes a voltage-generation circuit and a signal-generation circuit. The voltage-generation circuit receives an input signal and generates a first control voltage and a second control voltage. The signal-generation circuit is controlled by the first control voltage and a second control voltage to generate an output signal. A first delay time by which a falling edge of the output signal is delayed from a falling edge of the output signal is determined by the first control voltage. A second delay time by which a rising edge of the output signal is delayed from a rising edge of the output signal is determined by the second control voltage.Type: ApplicationFiled: September 23, 2016Publication date: March 29, 2018Applicant: Vanguard International Semiconductor CorporationInventors: Sheng-Chih CHUANG, Wei-Chung WU, Szu-Chi CHEN
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Patent number: 9806559Abstract: A reversible buck or boost converter is operable in a buck mode and in a boost mode. In the buck mode, the converter receives a supply voltage via an input terminal and generates a charging current that is supplied to a battery, thereby charging the battery. The supply voltage is also supplied through the converter to an output terminal. In a boost mode, the converter receives power form the battery and generates a supply current and voltage that is output onto the output terminal. The same single current sense resistor is used both to control the charging current in the buck mode and to control a constant current supplied to the output terminal in the boost mode. The output current is controlled to be constant, regardless of changes in the in the battery voltage and changes in the output voltage.Type: GrantFiled: October 13, 2015Date of Patent: October 31, 2017Assignee: Active-Semi, Inc.Inventors: Hong Mao, Wei-Chung Wu
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Patent number: 9391509Abstract: A switching regulator having fast start-up time and low standby power is disclosed. In an exemplary embodiment, an apparatus includes a transistor that generates a charging current at a first current level from a base current received at a base terminal. The apparatus also includes a capacitor that charges in response to the charging current at the first current level to generate a voltage signal that increases at a first rate. The apparatus also includes a charge pump having an output coupled to the base terminal. The charge pump outputs a charge pump current when the voltage signal exceeds a first voltage level. The base current is increased by charge pump current to cause the transistor to generate the charging current at a second current level, and the capacitor charges in response to the charging current at the second current level to generate the voltage signal that increases at a second rate.Type: GrantFiled: January 30, 2015Date of Patent: July 12, 2016Assignee: Active-Semi, Inc.Inventors: Wei-Chung Wu, Degang Xia, Rulong Jiang
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Publication number: 20160149484Abstract: A switching regulator having fast start-up time and low standby power is disclosed. In an exemplary embodiment, an apparatus includes a transistor that generates a charging current at a first current level from a base current received at a base terminal. The apparatus also includes a capacitor that charges in response to the charging current at the first current level to generate a voltage signal that increases at a first rate. The apparatus also includes a charge pump having an output coupled to the base terminal. The charge pump outputs a charge pump current when the voltage signal exceeds a first voltage level. The base current is increased by charge pump current to cause the transistor to generate the charging current at a second current level, and the capacitor charges in response to the charging current at the second current level to generate the voltage signal that increases at a second rate.Type: ApplicationFiled: January 30, 2015Publication date: May 26, 2016Inventors: Wei-Chung Wu, Degang Xia, Rulong Jiang
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Publication number: 20160036266Abstract: A reversible buck or boost converter is operable in a buck mode and in a boost mode. In the buck mode, the converter receives a supply voltage via an input terminal and generates a charging current that is supplied to a battery, thereby charging the battery. The supply voltage is also supplied through the converter to an output terminal. In a boost mode, the converter receives power form the battery and generates a supply current and voltage that is output onto the output terminal. The same single current sense resistor is used both to control the charging current in the buck mode and to control a constant current supplied to the output terminal in the boost mode. The output current is controlled to be constant, regardless of changes in the in the battery voltage and changes in the output voltage.Type: ApplicationFiled: October 13, 2015Publication date: February 4, 2016Inventors: Hong Mao, Wei-Chung Wu
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Patent number: 9178382Abstract: A reversible buck or boost converter is operable in a buck mode and in a boost mode. In the buck mode, the converter receives a supply voltage via an input terminal and generates a charging current that is supplied to a battery, thereby charging the battery. The supply voltage is also supplied through the converter to an output terminal. In a boost mode, the converter receives power from the battery and generates a supply current and voltage that is output onto the output terminal. The same single current sense resistor is used both to control the charging current in the buck mode and to control a constant current supplied to the output terminal in the boost mode. The output current is controlled to be constant, regardless of changes in the in the battery voltage and changes in the output voltage.Type: GrantFiled: August 12, 2013Date of Patent: November 3, 2015Assignee: Active-Semi, Inc.Inventors: Hong Mao, Wei-Chung Wu
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Publication number: 20150042292Abstract: A reversible buck or boost converter is operable in a buck mode and in a boost mode. In the buck mode, the converter receives a supply voltage via an input terminal and generates a charging current that is supplied to a battery, thereby charging the battery. The supply voltage is also supplied through the converter to an output terminal. In a boost mode, the converter receives power from the battery and generates a supply current and voltage that is output onto the output terminal. The same single current sense resistor is used both to control the charging current in the buck mode and to control a constant current supplied to the output terminal in the boost mode. The output current is controlled to be constant, regardless of changes in the in the battery voltage and changes in the output voltage.Type: ApplicationFiled: August 12, 2013Publication date: February 12, 2015Applicant: Active-Semi, Inc.Inventors: Hong Mao, Wei-Chung Wu
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Patent number: 8547003Abstract: A heat-dissipating module includes a plurality of cooling fins arranged radially, spaced apart from each other, and connected annularly in a manner that a hollow core is formed centrally in the heat-dissipating module. The cooling fins each bend at a preset position thereof and in a first direction, such that the cooling fins each include a first flap and a second flap. The first flap and the second flap together form a preset included angle therebetween.Type: GrantFiled: May 9, 2011Date of Patent: October 1, 2013Assignee: Fin-Core CorporationInventor: Wei Chung Wu
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Publication number: 20120195053Abstract: An LED lamp includes at least an LED unit, a heat-dissipating module, a substrate, a power module, a base, and a thermally insulating panel. The heat-dissipating module includes a plurality of cooling fins arranged radially, spaced apart from each other, and connected annularly. The LED unit is disposed on and coupled to the substrate. The substrate is disposed above the heat-dissipating module. The base is a hollow casing for accommodating the power module and the thermally insulating panel, and is coupled to the heat-dissipating module. The thermally insulating panel is inserted into a groove disposed on an inner edge of the base and positioned between the heat-dissipating module and the power module. The thermally insulating panel is spaced apart from the heat-dissipating module by an air-filled gap of a preset distance to insulate the heat generated by the LED unit and further protect the power module.Type: ApplicationFiled: May 9, 2011Publication date: August 2, 2012Inventor: Wei Chung Wu
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Publication number: 20120194055Abstract: A heat-dissipating module includes a plurality of cooling fins arranged radially, spaced apart from each other, and connected annularly in a manner that a hollow core is formed centrally in the heat-dissipating module. The cooling fins each bend at a preset position thereof and in a first direction, such that the cooling fins each include a first flap and a second flap. The first flap and the second flap together form a preset included angle therebetween.Type: ApplicationFiled: May 9, 2011Publication date: August 2, 2012Inventor: Wei Chung Wu
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Patent number: 8212400Abstract: A multi-rail power-supply system provides power to circuitry requiring at least one additional rail between a high and a low-voltage rail. The system comprises a first power regulator that interconnects the high-voltage rail and an intermediate node and sets a first voltage rail that has a magnitude that is less than the high-voltage rail, wherein current that flows from the high-voltage rail is employed by a first set of peripheral circuitry prior to sinking through the first power regulator to the intermediate node. The system further comprises a second power regulator that interconnects the intermediate node and the low-voltage rail and sets a second voltage rail that has a magnitude that is greater than the low-voltage rail, wherein current that flows from the intermediate node is sourced by the second regulator and is employed by a second set of peripheral circuitry prior to flowing to the low-voltage rail.Type: GrantFiled: June 1, 2009Date of Patent: July 3, 2012Assignee: Texas Instruments IncorporatedInventors: Wei-Chung Wu, Paul Vulpoiu
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Publication number: 20110193539Abstract: A switching regulator generally includes an output circuit, a comparator, an on-time timer and an error amplifier. The output circuit receives an input voltage and produces an output voltage. The comparator causes the output circuit to turn on the output voltage when a feedback voltage falls below a first reference voltage. The on-time timer causes the output circuit to turn off the output voltage after a time-out period. The error amplifier receives the feedback voltage and a second reference voltage and produces the first reference voltage.Type: ApplicationFiled: February 10, 2010Publication date: August 11, 2011Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Thomas A. Schmidt, Robert Martinez, Wenliang Chen, Wei-Chung Wu
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Patent number: 7948316Abstract: An amplifier is provided that includes an output portion that sources and sinks current associated with an output load and an amplification portion that is biased by a relatively small bias current with respect to an output current of the amplifier. The amplification portion provides an amplified output signal to the output portion. The amplifier further comprises at least one impedance component coupled between the output portion and the amplification portion to alter at least one pole associated with the amplifier to mitigate instability of the amplifier related to the relatively small bias current.Type: GrantFiled: May 28, 2009Date of Patent: May 24, 2011Assignee: Texas Instruments IncorporatedInventors: Wei-Chung Wu, Lin Chen, Yuan Gu, Kae Ann Wong