Abstract: Disclosed herein is a plug feature for an electronic device. More specifically, the plug feature described herein is used to plug, fill or otherwise seal an aperture associated with a SIM tray of an electronic device. The plug feature may be coupled to an ejection mechanism and may extend at least partially into an aperture defined by the SIM tray and/or an aperture defined by the housing of the electronic device.

Abstract: An electronic device may include a housing and at least one coil carried by the housing. The electronic device may include a field member that includes a magnetic body having a shaft-receiving passageway therein, and at least one bearing within the shaft-receiving passageway. A shaft extends through the at least one bearing and coupled to the housing to permit reciprocal movement of the field member along the shaft and within the housing responsive to the at least one coil. A controller may be capable of powering the at least one coil to move the field member after a threshold period of non-movement.

Abstract: An electronic device includes at least one screen. One or more bumpers are moveable between at least a stowed position where the bumper is flush or below the screen and a deployed position where at least a portion of the bumper projects above the screen. One or more sensors detect when the electronic device is subject to one or more drop events. When a drop event is detected, the bumper moves to the deployed position, protecting the screen. In various implementations, the bumper may be moveable by a push-push mechanism or a magnet assisted actuator mechanism. In other implementations, the bumper may include piezoelectric material to which voltage can be applied to move the bumper.

Abstract: Disclosed herein is a plug feature for an electronic device. More specifically, the plug feature described herein is used to plug, fill or otherwise seal an aperture associated with a SIM tray of an electronic device. The plug feature may be coupled to an ejection mechanism and may extend at least partially into an aperture defined by the SIM tray and/or an aperture defined by the housing of the electronic device.

Abstract: An electronic device includes at least one screen. One or more bumpers are moveable between at least a stowed position where the bumper is flush or below the screen and a deployed position where at least a portion of the bumper projects above the screen. One or more sensors detect when the electronic device is subject to one or more drop events. When a drop event is detected, the bumper moves to the deployed position, protecting the screen. In various implementations, the bumper may be moveable by a push-push mechanism or a magnet assisted actuator mechanism. In other implementations, the bumper may include piezoelectric material to which voltage can be applied to move the bumper.

Abstract: In one aspect, the present invention comprises an electrostatic discharge (ESD) protection circuit comprising a plurality of input circuits in which each input circuit comprises a first PMOS and a first NMOS transistor connected in series between a power supply and ground and first and second inverters connected to the gates of the first PMOS and NMOS transistors. Each inverter connected to the gate of the first NMOS transistor comprises a second NMOS transistor connected between that gate and ground and the ratio of the width of the gate of the second NMOS transistor to the width of the gate of the first NMOS transistor of each of the input circuits is substantially the same. In another aspect of the invention, a multi-fingered gate transistor is formed in a first well of one conductivity type that is surrounded by a second well of the same conductivity type from which it is separated by a shallow trench isolation and a portion of the substrate.

Abstract: In one aspect, the present invention comprises an electrostatic discharge (ESD) protection circuit comprising a plurality of input circuits in which each input circuit comprises a first PMOS and a first NMOS transistor connected in series between a power supply and ground and first and second inverters connected to the gates of the first PMOS and NMOS transistors. Each inverter connected to the gate of the first NMOS transistor comprises a second NMOS transistor connected between that gate and ground and the ratio of the width of the gate of the second NMOS transistor to the width of the gate of the first NMOS transistor of each of the input circuits is substantially the same. In another aspect of the invention, a multi-fingered gate transistor is formed in a first well of one conductivity type that is surrounded by a second well of the same conductivity type from which it is separated by a shallow trench isolation and a portion of the substrate.

Abstract: The present invention provides an ESD device for protecting thin oxide layers in transistors or capacitors in an integrated circuit. In one embodiment, the ESD device includes a silicon-controlled rectifier (SCR), the SCR including a PNP bipolar transistor and a NPN bipolar transistor. The ESD device further includes first and second trigger devices coupled to the SCR and configured to simultaneously turn on the PNP bipolar transistor and the NPN bipolar transistor in response to an ESD pulse on the ESD device. The base of the NPN bipolar transistor is floating to allow a first external resistor to be connected between the base and emitter of the NPN bipolar transistor. A second external resistor can be connected between the base and emitter of the PNP bipolar transistor.

Abstract: An apparatus performs reliability assessment of electronic hardware. The apparatus includes a test assembly. The test assembly includes at least one programmable logic device (PLD). The PLD is configured to provide a logic function, such as the function of a plurality of inverters coupled in a cascade manner. The apparatus further includes a signal source coupled to the test assembly. The signal source provides a stimulus signal to the test assembly. The apparatus also includes a signal monitor coupled to the test assembly. The signal monitor monitors a response signal generated by the test assembly.