Abstract: A data storage device and methods of manufacture are provided which tend to protect the device against moisture and shock. The device includes a circuit board, a coating, a housing, and preferably a sealant. The circuit board is in electrical communication with an electrical interface. The coating is disposed at least on the circuit board to generally encapsulate the circuit board. The housing is sized and configured to generally encompass the circuit board and the coating. The housing includes a housing opening being sized and configured with the electrical interface being at least partially exposed therethrough. The sealant is preferably disposed within the housing substantially intermediate the interior surface of the housing and the coating on the circuit board. Further, at least one of the coating and the sealant may be disposed substantially intermediate the electrical interface and the housing opening.

Abstract: A method is disclosed for making a leadframe package stand having application in semiconductor packaging and microelectronic assembly in which an IC device (e.g., a bare chip IC, a wafer level package, or a chipscale package) is received for electrical connection to a PWB or for vertical package over package stacking. Electrically conductive leadframe traces are arranged in an area array circuit pattern between outer leads at the periphery of the mold body of a leadframe for connection to the PWB to inner leads for connection to the IC device. The inner lead tips terminate at each side of the IC device in groups of parallel aligned rows and columns to facilitate connection to the IC device without using intermediate bonding wires. Prior to molding, the inner leads of the conductive traces are secured by sacrificial tie-bars or adhesive tape to prevent movement of the inner leads and possible short circuits during molding. A cavity is formed in the mold body during molding so as to lie above the inner leads.

Abstract: A thin, small outline IC leadframe plastic package to be used to assemble high performance, high speed semiconductor memory IC devices such as dynamic random access memories (DRAM) having a high data transfer rate in the range of 1 GigaHertz. The package leadframe is electrically interconnected to the IC device input-output pads by either electrically conductive (e.g. solder) bumps that are flip-chip bonded to the IC device or by of an interposer. The interposer contains integral curled micro-spring contacts at opposite ends of conductive fan out traces. The interposer is attached to the leadframe bonding pads by way of tape automated bonding, soldering, or adhesive bonding. The leadframe that is interconnected to the IC device by the aforementioned flip-chip bumps or the interposer is encapsulated and trimmed to form either gull-wing style perimeter leads as a standard thin small outline package (TSOP) or wrap around leads as a micro-leadframe (MLF) package.

Abstract: A data storage device and methods of manufacture are provided which tend to protect the device against moisture and shock. The device includes a circuit board, a coating, a housing, and preferably a sealant. The circuit board is in electrical communication with an electrical interface. The coating is disposed at least on the circuit board to generally encapsulate the circuit board. The housing is sized and configured to generally encompass the circuit board and the coating. The housing includes a housing opening being sized and configured with the electrical interface being at least partially exposed therethrough. The sealant is preferably disposed within the housing substantially intermediate the interior surface of the housing and the coating on the circuit board. Further, at least one of the coating and the sealant may be disposed substantially intermediate the electrical interface and the housing opening.

Abstract: A dual in-line memory module (DIMM) and a digital flash card are disclosed including an internal, built-in RFID tag in which identification and product information is contained. The RFID tag has an RF integrated circuit chip and antenna traces spreading outwardly therefrom to permit access to the information contained by the RF chip. In the case of a DIMM, the RF integrated circuit chip and its antenna traces are located on top of or between the layers of a multi-layer laminated printed wiring board substrate. In the case of a digital flash card, the RF integrated circuit chip and its antenna traces are preferably located on top of a multi-layer printed wiring board substrate and then encapsulated within a molded cover. In the alternative, the RF chip and its antenna traces are attached to the inside of a cover that extends over and is spaced above the printed wiring board substrate.

Abstract: A method for molding digital storage memory cards such as, for example, multimedia cards (MMC), secure digital cards (SD), and similar small form factor digital memory cards. A PCA subassembly including, for example, a leadframe (TSOP) package for enclosing a flash IC and a (e.g., land grad array) controller package for enclosing a controller IC are mounted on a printed wiring board within a mold cavity. A high melt flow index resin is injected into the mold cavity to form an integral, solid body within which to completely encapsulate the flash IC and controller packages and form a cover over top the flash IC package so as to maintain the required memory card height tolerance. In one embodiment, the resin material is injected downwardly into the mold cavity from locations above the respective rows of leads of the flash IC package.

Abstract: A high density memory card assembly having application for USB drive storage, flash and ROM memory cards, and similar memory card formats. A cavity is formed through a rigid laminate substrate. First and second digital memory devices (e.g., TSOP packages or bare semiconductor dies) are located within the cavity so as to be recessed relative to the top and bottom of the substrate. The recessed first and second memory devices are arranged in spaced, face-to-face alignment with one another within the cavity. The first and second memory devices are covered and protected by respective first and second memory packages that are located on the top and bottom of the substrate. By virtue of the foregoing, the memory package density of the assembly can be increased without increasing the height or area consumed by the assembly for receipt within an existing external housing.

Abstract: A thin, small outline IC leadframe plastic package to be used to assemble high performance, high speed semiconductor memory IC devices such as dynamic random access memories (DRAM) having a high data transfer rate in the range of 1 GigaHertz. The package leadframe is electrically interconnected to the IC device input-output pads by either electrically conductive (e.g. solder) bumps that are flip-chip bonded to the IC device or by of an interposer. The interposer contains integral curled micro-spring contacts at opposite ends of conductive fan out traces. The interposer is attached to the leadframe bonding pads by way of tape automated bonding, soldering, or adhesive bonding. The leadframe that is interconnected to the IC device by the aforementioned flip-chip bumps or the interposer is encapsulated and trimmed to form either gull-wing style perimeter leads as a standard thin small outline package (TSOP) or wrap around leads as a micro-leadframe (MLF) package.

Abstract: A high density, low profile, three dimensional memory module having multi-level semiconductor packages mounted on one or opposite sides of a printed wiring board. Each multi-level package of the memory module contains an upper level DRAM integrated circuit package that is surface mounted on the printed wiring board and at least one lower level DRAM integrated circuit package that is surface mounted on the printed wiring board below the upper level package, such that the upper and lower level packages are stacked one above the other. The upper level package is preferably a thin small outline package, and the lower level package is preferably a leadless chip scale package. The leads of the upper level package are of sufficient length so that the standoff height of the upper level package establishes a clearance thereunder in which to receive the lower level package.

Abstract: A vertically integrated chip scale package (CSP) assembly comprising two or more single chip package subassemblies having an upper level CSP subassembly superimposed directly above a lower level CSP subassembly. The lower-most CSP subassembly in the vertical stack contains an array of solder balls for interconnection to a printed wiring board. The vertical electrical connection between the upper and lower level package subassemblies is accomplished by using wire bonding from perimeter wire bonding pads located on an upper level substrate extension to matching perimeter wire bonding pads located on a lower level substrate extension that is longer in length than the upper level substrate extension. The stacked package subassemblies are bonded together by using a thin adhesive material, and the perimeter wire bonds are encapsulated by an encapsulant for protection.

Abstract: A high density, low profile, three dimensional memory module having multi-level semiconductor packages mounted on one or opposite sides of a printed wiring board. Each multi-level package of the memory module contains an upper level DRAM integrated circuit package that is surface mounted on the printed wiring board and at least one lower level DRAM integrated circuit package that is surface mounted on the printed wiring board below the upper level package, such that the upper and lower level packages are stacked one above the other. The upper level package is preferably a thin small outline package, and the lower level package is preferably a leadless chip scale package. The leads of the upper level package are of sufficient length so that the standoff height of the upper level package establishes a clearance thereunder in which to receive the lower level package.

Abstract: The present invention discloses a new substrate with two metal layer circuit structure and layout for semiconductor packaging. The speed and performance characteristics of the semiconductor device are optimized while the packaging structure is simplified by utilizing only one dielectric layer and conventional printed circuit board fabrication process. The difficulties encountered due to the complexities and higher cost of production required for the multiple layer and high density configuration are thus avoided. The improved circuit structure is achieved by implementing a segmented ring on one side of a substrate and a split plane on the other side thus forming a single layer substrate structure. The edges of the substrate are coated with metal layer to provide inter-layer connections.

Abstract: A method for forming a conductive vias in a non-conductive substrate having a through-hole formed therein intermediate two side thereof. The method utilizes the steps of: applying gold paste to the through-hole so as to provide electrical conduction therethrough; and under firing the gold paste when a thin conductive film is present upon the substrate and fully firing the gold paste when no thin conductive film is present on the substrate. Under firing the gold paste when a thin-film is present upon the substrate prevents degradation of the thin conductive film. Subsequent processing of the gold paste assures the integrity and reliability thereof. Thus, the gold paste provides enhanced conductivity and improved reliability, as compared to contemporary thin-film vias.

Abstract: A method for forming a conductive vias in a non-conductive substrate having a through-hole formed therein intermediate two side thereof. The method utilizes the steps of: applying gold paste to the through-hole so as to provide electrical conduction therethrough; and under firing the gold paste when a thin conductive film is present upon the substrate and fully firing the gold paste when no thin conductive film is present on the substrate. Under firing the gold paste when a thin-film is present upon the substrate prevents degradation of the thin conductive film. Subsequent processing of the gold paste assures the integrity and reliability thereof. Thus, the gold paste provides enhanced conductivity and improved reliability, as compared to contemporary thin-film vias.

Abstract: A method for forming conductive via interconnects utilizes the steps of: applying a sacrificial coating to at least one surface of a substrate; laser drilling the substrate through the sacrificial coating to form a via through-hole; applying a conductive coating to the via through-hole; and removing the sacrificial coating(s). Recasting and shattering thus occur in the sacrificial coating rather than in the substrate during the step of laser drilling so as to enhance via through-hole geometry.

Abstract: A substrate for attaching infrared detector elements to multi-layer modules has a detector interface member to which the infrared detector elements are attachable and which is attachable to the multi-layer module so as to provide electrical communication between the infrared detector elements and the multi-layer module. At least one removable tab is formed upon the detector interface member and a plurality of probing pads are formed upon each tab. Conductive conduits formed upon each tab extend from the detector interface member to the probing pads so as to facilitate electrical communication between dedicated ones of the infrared detector elements and dedicated ones of the probing pads. The probing pads facilitate electrical testing of individual infrared detector elements.

Abstract: A multi-directional infrared detector system provides multi-view or surround-view imaging which is particularly suited for use in tactical battlefield situations. The system utilizes a plurality of infrared detector arrays disposed in a generally circular configuration, each of the infrared detector arrays having a plurality of infrared detector elements formed thereon; a corresponding plurality of dedicated optics assemblies for forming images upon the infrared detector arrays; and at least one conductive conduit supporting layer having conductive conduits formed thereon. The conductive conduit support layer extends inwardly from each of the infrared detector arrays to a core defined by the infrared detector arrays. Signal conditioning circuitry is disposed generally at the core of the infrared detector arrays such that signals representative of the outputs of the infrared detector elements are communicated from the detector elements to the signal processing circuitry via the conductive conduits.

Abstract: A precisely spaced stack of substrate layers comprises a plurality of substrate layers disposed one above another in a stacked configuration and having a glass layer coating on one of each pair of adjacent substrates, the glass layer having a thickness such that the sum of the thicknesses of the glass layer and the substrate to which the glass layer is fused is approximately equal for substantially all of the substrate layers. A polymer adhesive is disposed intermediate the glass layer and a substrate layer such that adjacent substrate layers are bonded together. By controlling the height of each pair of substrate and glass layers, a precisely spaced and strongly bonded stack of substrate layers is formed.

Abstract: An infrared detector subarray having an integral filter assembly is comprised of a plurality of stacked modules defining an infrared detector focal plane subarray; a filter plate sized and configured to correspond to the infrared detector subarray; and a plurality of supports disposed intermediate the filter plate and the detector subarray for attaching the filter plate to the subarray such that the filter plate is in close proximity to the detector subarray. Scattering and crossstalk are minimized by positioning the filter plate in close proximity to the detector subarray. The supports may comprise planar members having a thickness of less than approximately 0.003 inch such that they may be disposed intermediate adjacent modules.

Abstract: A fused high density multi-layered integrated circuit module for integrating infrared detector arrays to signal conditioning circuits is disclosed. The module comprises a plurality of thin film substrate layers disposed in substantially overlapping registry to form a non-conductive supporting body, a plurality of the layers have electronic devices mounted thereon. A plurality of detector element connectors are formed along a first edge portion of the body. Conductive conduits are formed upon a plurality of the layers. The conductive conduits have first portions which interconnect the detector element connectors to the electronic devices disposed upon the layers of the body. The conductive conduits also have second portions formed upon the surface of said layers and extending to the second edge portion thereof for communicating signals between the electronic devices and external electronics. A glass binding material adhesively attaches adjacent substrate layers together.