Abstract: A method for forming a semiconductor package is provided. The method includes forming a first alignment mark in a first substrate of a first wafer and forming a first bonding structure over the first substrate. The method also includes forming a second bonding structure over a second substrate of a second wafer and trimming the second substrate, so that a first width of the first substrate is greater than a second width of the second substrate. The method further includes attaching the second wafer to the first wafer via the first bonding structure and the second bonding structure, thinning the second wafer until a through-substrate via in the second substrate is exposed, and performing a photolithography process on the second wafer using the first alignment mark.

Abstract: A die includes a substrate, a conductive pad, a connector and a protection layer. The conductive pad is disposed over the substrate. The connector is disposed on the conductive pad. The connector includes a seed layer and a conductive post. The protection layer laterally covers the connector. Topmost surfaces of the seed layer and the conductive post and a top surface of the protection layer are level with each other.

Abstract: A semiconductor device includes: a substrate, including an upper surface and a first to a fourth side surfaces; wherein the upper surface includes a first edge connecting the first side surface and a second edge opposite to the first edge and connecting the second side surface; a first modified trace formed on the first side surface; and a semiconductor stack formed on the upper surface, including a lower surface connecting the upper surface of the substrate, and the lower surface comprises a fifth edge adjacent to the first edge and a sixth edge opposite to the fifth edge and adjacent to the second edge; wherein a shortest distance between the first edge and the fifth edge is S1 ?m, and a shortest distance between the second edge and the sixth edge is S2 ?m; wherein in a lateral view viewing from the third side surface, the first side surface forms a first acute angle with a degree of ?1 with the vertical direction, the second side surface forms a second acute angle with a degree of ?2 with the vertical dire

Abstract: An analysis method and an electronic apparatus for breast image are provided. The method includes the following steps. One or more breast ultrasound images are obtained. The breast ultrasound images are used for forming a three-dimensional (3D) breast model. A volume of interest (VOI) in the breast ultrasound image is obtained by applying a detection model on the 3D breast model. The VOI is compared with a tissue segmentation result. The VOI is determined as a false positive according to a compared result between the VOI and the tissue segmentation result. The compared result includes that the VOI is located at a glandular tissue based on the tissue segmentation result. In response to the VOI being located in the glandular tissue of the tissue segmentation result, the VOI is compared with the lactiferous duct in the 3D breast model.

Abstract: The present invention relates to a fluorine-containing resin composition, and a resin vanish, a fluorine-containing dielectric sheet, a laminate, a copper clad laminate and a printed circuit board containing the same. The fluorine-containing resin composition comprises 30 wt. %-70 wt. % of a fluorine-containing polymer, 30 wt. %-70 wt. % of an inorganic filler which includes the following particle size distribution: D10 is greater than 1.5 ?m; and D50 is 10-15 ?m. In the present invention, the selection of an inorganic filler with a specific particle size distribution can ensure that the boards prepared by the fluorine-containing resin composition have excellent dielectric properties and voltage resistance performance, even if the inorganic filler is added in a large amount.

Abstract: Disclosed are a foldable screen and a display device. The foldable screen includes: a flexible display panel and a plurality of elastic portions, wherein each of the elastic portions includes each of elastic support members and two connecting rods fixedly connected to each of the elastic support members; wherein the two connecting rods are respectively connected to two flat portions of the flexible display panel, and the elastic support members are configured to supply a support force to the foldable portion in the case that a display surface of the foldable portion of the flexible display panel is coplanar with those of the flat portions.

Abstract: A package structure and method of forming the same are provided. The package structure includes a polymer layer, a redistribution layer, a die, and an adhesion promoter layer. The redistribution layer is disposed over the polymer layer. The die is sandwiched between the polymer layer and the redistribution layer. The adhesion promoter layer, an oxide layer, a through via, and an encapsulant are sandwiched between the polymer layer and the redistribution layer. The encapsulant is laterally encapsulates the die. The through via extends through the encapsulant. The adhesion promoter layer and the oxide layer are laterally sandwiched between the through via and the encapsulant. A bottom portion of the encapsulant is longitudinally sandwiched between the adhesion promoter layer and the polymer layer.

Abstract: Techniques are described to determine a time clock value by a communication device using information provided by a network device. An example wireless communication method includes receiving, by a communication device, a first signal in a first time period; transmitting, by the communication device, a second signal in a second time period later than the first time period to a network device; receiving, by the communication device, a third message comprising a timing information associated with the first time period, the second time period, or a propagation delay value; and determining, by the communication device, a time when the communication device receives the first signal based at least on the timing information.

Abstract: A circuit board assembly is applied to the field of electronic communications technologies to resolve a prior-art heat dissipation problem of a circuit board. The circuit board assembly combines, on a second circuit board, low-speed signals transmitted between a plurality of I/O modules and an IC chip, and then transmits the combined low-speed signals to the IC chip by using a low-speed cable. A low-speed signal sent by the IC chip to the plurality of I/O modules is extended to a plurality of low-speed signals on the second circuit board, and then the plurality of low-speed signals are separately sent to the plurality of I/O modules. This may be applied to a scenario in which a relatively large quantity of electronic components need to be disposed on a circuit board.

Abstract: Methods, apparatus, and systems that facilitate the indication of the codebook to be transmitted/retransmitted are disclosed. In one example aspect, a method for wireless communication includes transmitting, by a base station, a physical-layer control signaling message to a user device triggering a retransmission of a codebook for a feedback transmission that has been previously canceled. The physical-layer control signaling message includes a field of resource assignment that is used to indicate an attribute associated with the codebook. The method also includes receiving, by the base station, the retransmission of the codebook from the user device according to the physical-layer control signaling message.

Abstract: A semiconductor device includes a semiconductor substrate; a plurality of channel regions, including a p-type channel region and an n-type channel region, disposed over the semiconductor substrate; and a gate structure. The gate structure includes a gate dielectric layer disposed over the plurality of channel regions and a work function metal (WFM) structure disposed over the gate dielectric layer. The WFM structure includes an n-type WFM layer over the n-type channel region and not over the p-type channel region and further includes a p-type WFM layer over both the n-type WFM layer and the p-type channel region. The gate structure further includes a fill metal layer disposed over the WFM structure and in direct contact with the p-type WFM layer.

Abstract: An image sensor structure includes a semiconductor substrate, a plurality of image sensing elements, a reflective element, and a high-k dielectric structure. The image sensing elements are in the semiconductor substrate. The reflective element is in the semiconductor substrate and between the image sensing elements. The high-k dielectric structure is between the reflective element and the image sensing elements.

Abstract: A pellicle for an extreme ultraviolet (EUV) photomask includes a pellicle frame and a main membrane attached to the pellicle frame. The main membrane includes a plurality of nanotubes, and each of the plurality of nanotubes is covered by a coating layer containing Si and one or more metal elements.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes an interconnection structure over a semiconductor substrate and a conductive pillar over the interconnection structure. The conductive pillar has a protruding portion extending towards the semiconductor substrate from a lower surface of the conductive pillar. The semiconductor device structure also includes an upper conductive via between the conductive pillar and the interconnection structure and a lower conductive via between the upper conductive via and the interconnection structure. The lower conductive via is electrically connected to the conductive pillar through the upper conductive via. The conductive pillar extends across opposite sidewalls of the upper conductive via and opposite sidewalls of the lower conductive via. A top view of an entirety of the second conductive via is separated from a top view of an entirety of the protruding portion.

Abstract: A flexible package is provided. The flexible package includes a first carrier and a second carrier. The second carrier is electrically connected to the first carrier. The second carrier is at least partially embedded in the first carrier, and an electrical connection interface between the first carrier and the second carrier is within the first carrier.

Abstract: Techniques are described for hybrid automatic repeat request acknowledgement (HARQ-ACK) information generation techniques for group common shared channels, such as one or more physical downlink shared channels (PDSCHs).

Abstract: The present disclosure describes methods, system, and devices for collision resolution in configuring time-frequency resource in a half-duplex and/or full-duplex telecommunication system. The method includes receiving, by a user equipment (UE), a first message which is used to resolve a collision between a first transmission in a first frequency resource region and a second transmission in a second frequency resource region, wherein the first and second transmissions overlap in a time domain; and determining, by the UE based on the first message, to transmit one of the first transmission and the second transmission, wherein transmission directions of the first transmission and the second transmission are different.

Abstract: A fan cage assembly includes a cage and a handle mechanism, the handle mechanism includes a mount member including a mount portion and an extension portion respectively located at different sides of the cage and an operative member movably disposed on the extension portion of the mount member.

Abstract: Techniques are described to supporting transmission on any serving cell, carrier, or bandwidth part (BWP). An example wireless communication method includes receiving, by a first device from a second device, a first control information that schedules a first transmission on a first cell with the first device, where the first control information indicates a first hybrid automatic repeat request (HARQ) entity associated with the first transmission; and performing an operation to process the first control information.

Abstract: A method of manufacturing a semiconductor device includes forming a first layer of a first planarizing material over a patterned surface of a substrate, forming a second layer of a second planarizing material over the first planarizing layer, crosslinking a portion of the first planarizing material and a portion of the second planarizing material, and removing a portion of the second planarizing material that is not crosslinked. In an embodiment, the method further includes forming a third layer of a third planarizing material over the second planarizing material after removing the portion of the second planarizing material that is not crosslinked. The third planarizing material can include a bottom anti-reflective coating or a spin-on carbon, and an acid or an acid generator. The first planarizing material can include a spin-on carbon, and an acid, a thermal acid generator or a photoacid generator.