Abstract: A method includes forming a first metallic feature, forming a dielectric layer over the first metallic feature, etching the dielectric layer to form an opening, with a top surface of the first metallic feature being exposed through the opening, and performing a first treatment on the top surface of the first metallic feature. The first treatment is performed through the opening, and the first treatment is performed using a first process gas. After the first treatment, a second treatment is performed through the opening, and the second treatment is performed using a second process gas different from the first process gas. A second metallic feature is deposited in the opening.

Abstract: The present invention provides a voltage control method for controlling a power supply. The voltage control method comprises the following steps: obtaining a present output voltage value associated with a present gain value; obtaining a predetermined output voltage value associated with a predetermined duty ratio; calculating a target gain value, corresponding to the predetermined duty ratio, according to a gain value formula; performing a weight calculation on the present gain value and the target gain value for generating a buffer gain value; and setting an output voltage command according to the buffer gain value. Wherein the buffer gain value is between the present gain value and the target gain value.

Abstract: A layout includes a first and a second standard cells abutting along a boundary line. The first cell includes first fins. An edge of the first fins closest to and away from the boundary line by a distance D1. A first gate line over-crossing the first fins protrudes from the edge by a length L1. The second cell includes second fins. An edge of the second fins closest to and away from the boundary line by a distance D2. A second gate line over-crossing the second fins protrudes from the edge by a length L2. Two first dummy gate lines at two sides of the first fins and two second dummy lines at two sides of the second fins are respectively away from the boundary line by a distance S. The lengths L1 and L2, the distances S, D1 and D2 have the relationships: L1?D1?S, L2?D2?S, and D1?D2.

Abstract: Provided are pamoate salts of ketamine having a stoichiometry of 2:1 of ketamine to pamoate, including R, S-ketamine pamoate, S-ketamine pamoate, or R-ketamine pamoate, and crystalline or amorphous forms of the pamoate salts, and having excellent safety and properties for pharmaceutical applications. Also provided are pharmaceutical compositions including the pamoate salts of ketamine and their uses in treating a CNS disease or serving as an anesthetic.

Abstract: A carrier for different form factors for insertion in a slot of a computing device is disclosed. The different form factors have different thicknesses defined by the E1.S specification. The carrier includes a base holding a first type of form factor. A bezel is configurable for insertion in a slot for a device of the first type of form factor. The bezel has an attachment surface. The base is attachable to the attachment surface of the bezel. A second type of form factor is also attachable to the attachment surface of the bezel. A cover encloses the first type of form factor when joined to the base. The base and cover are discarded when the second type of form factor is attached to the bezel. The attached bezel and second type of form factor may also be inserted in the slot.

Abstract: A display panel including a circuit board, a plurality of bonding pads, a plurality of light emitting devices, and a plurality of solder patterns is provided. The bonding pads are disposed on the circuit board, and each includes a first metal layer and a second metal layer. The second metal layer is located between the first metal layer and the circuit board. The first metal layer includes an opening overlapping the second metal layer. A material of the first metal layer is different from a material of the second metal layer. The light emitting devices are electrically bonded to the bonding pads. Each of the solder patterns electrically connects one of the light emitting devices and one of the bonding pads. The solder patterns each contact the second metal layer through the opening of the first metal layer of one of the bonding pads to form a eutectic bonding.

Abstract: A case is provided, including a shell, a fan frame, and a fan module. The shell is internally provided with a backplane and a motherboard, where the motherboard is connected to the backplane along a first axis, the backplane is connected with a plug connector, the plug connector includes a plug connector body and a plurality of connection terminals, and the connection terminals are located in the plug connector body. The fan frame bears the fan module, and the fan module includes a fan assembly and a matching connector. The matching connector is connected to the fan assembly, and the matching connector is connected to the plug connector along a second axis. The matching connector includes a matching connector body and a plurality of matching terminals, and the matching terminals are located in the matching connector body. The fan frame is fixed in the shell.

Abstract: A sewing machine includes a main body and a quick release needle plate module. The main body includes a base seat having an inner frame, and an outer case that is mounted to the inner frame and that defines an accommodating compartment. The quick release needle plate module includes a catch member, and a needle plate that covers the accommodating compartment, that is detachably pivoted to a rear section of the inner frame, and that engages the catch member. The quick release needle plate module further includes a press member inserted through the outer case and the inner frame, and operable to push the catch member to disengage the catch member. The needle plate has a plate body that covers the accommodating compartment, and a resilient member mounted between the inner frame and the plate body for driving pivot action of the plate body away from the inner frame.

Abstract: A method for manufacturing a semiconductor structure is provided. A substrate including a fin structure is received, provided or formed. A sacrificial gate layer is formed over the fin structure and a source/drain structure is formed adjacent to the sacrificial gate layer, wherein the sacrificial gate layer is surrounded by a dielectric structure. The sacrificial gate layer is removed, wherein a recess is defined by the dielectric structure. A work function layer is formed in the recess, wherein the work function layer includes an overhang portion at an opening of the recess. A thickness of the work function layer is reduced. A glue layer is formed over the work function layer. A semiconductor structure thereof is also provided.

Abstract: A package structure and the manufacturing method thereof are provided. The package structure includes a first package including at least one first semiconductor die encapsulated in an insulating encapsulation and through insulator vias electrically connected to the at least one first semiconductor die, a second package including at least one second semiconductor die and conductive pads electrically connected to the at least one second semiconductor die, and solder joints located between the first package and the second package. The through insulator vias are encapsulated in the insulating encapsulation. The first package and the second package are electrically connected through the solder joints. A maximum size of the solder joints is greater than a maximum size of the through insulator vias measuring along a horizontal direction, and is greater than or substantially equal to a maximum size of the conductive pads measuring along the horizontal direction.

Abstract: An anti-glare film is disclosed. The anti-glare film comprises a transparent substrate and an anti-glare layer comprising an acrylic binder resin, a polyether-modified siloxane and a plurality of silica nanoparticles, wherein the silica nanoparticles are flocculated into a micro-floccule with an average secondary particle diameter of 1,500 nm to 3,100 nm. The present anti-glare film can provide a reliable anti-glare property with low haze and fine surface.

Abstract: An anti-glare film is disclosed. The anti-glare film comprises a poly(methyl methacrylate) (PMMA) base film and an anti-glare layer comprising an acrylic binder resin and organic microparticles, wherein the anti-glare layer comprises an miscible sub-layer adjacent to the interface between the anti-glare layer and the base film for urging the organic microparticles toward the upper portion of the anti-glare layer to form an anti-glare sub-layer with an uneven surface and wherein the average thickness of the miscible layer is at least 40 percent of the total thickness of the anti-glare layer and a ratio of the average thickness of the anti-glare sub-layer to the diameter of the microparticle is between 0.45 to 1.1.

Abstract: An anti-glare film is disclosed. The anti-glare film comprises a transparent substrate and an anti-glare layer comprising an acrylic binder resin, a polyether-modified siloxane and a plurality of silica nanoparticles, wherein the silica nanoparticles are flocculated into a micro-floccule with an average secondary particle diameter of 1,500 nm to 3,100 nm. The present anti-glare film can provide a reliable anti-glare property with low haze and fine surface.

Abstract: An anti-glare film is disclosed. The anti-glare film comprises a transparent substrate and an anti-glare layer comprising an acrylic binder resin, an acrylate-ether-group-containing surface active agent and a plurality of silica nanoparticles, wherein the silica nanoparticles are flocculated into a micro-floccule with an average secondary particle diameter of 1,600 nm to 3,300 nm. The present anti-glare film can provide a reliable anti-glare property with a low haze.

Abstract: An anti-glare film is disclosed. The anti-glare film comprises a poly(methyl methacrylate) (PMMA) base film and an anti-glare layer comprising an acrylic binder resin and organic microparticles, wherein the anti-glare layer comprises an miscible sub-layer adjacent to the interface between the anti-glare layer and the base film for urging the organic microparticles toward the upper portion of the anti-glare layer to form an anti-glare sub-layer with an uneven surface and wherein the average thickness of the miscible layer is at least 40 percent of the total thickness of the anti-glare layer and a ratio of the average thickness of the anti-glare sub-layer to the diameter of the microparticle is between 0.45 to 1.1.

Abstract: 3D reality rendering technology is embodied in computational apparatus and automated process for interior space design, with which combinations of interior space design elements can be extracted, saved, and be applied to other spaces. A system and data structure for saving and loading coded elements are created to allow design elements to be applied into new projects where these elements form new space characteristics. Thus, time-consuming limitations of conventional 3D design software are overcome, for example, by enabling repetition of same working process in allocating design elements into the interior space. In this way, design elements are not rebuilt or allocated manually for every project, and preferably only material or shape of elements may be changed. Furthermore, by using internet and 3D rendering technologies to share combinations of interior design elements to other user's design project, the design process is shortened to save time.

Abstract: A low noise amplifier with back-to-back connected diodes and a back-to-back connected diode with high impedance thereof are provided. The low noise amplifier includes a first operational amplifier (OP) and at least two first back-to-back connected diodes. The back-to-back connected diode with high impedance is formed from at least one MOS FET operated within a cut-off region. The first back-to-back connected diodes are connected electrically between the first input end and the first output end, and between the second input end and the second output end, of the first OP respectively. By the implementation of the present invention, the low noise amplifier is not only low noise, but also with low energy consumption, high stability, low circuitry complexity, and easily controlled manufacturing process.

Abstract: A current-mode analog baseband apparatus is provided. The apparatus includes a current-mode low-order filter, a current-mode programmable gain amplifier (PGA) unit and a high-order filter. The input impedance is smaller than the output impedance in the current-mode low-order filter. An input terminal of the current-mode PGA unit is connected to an output terminal of the current-mode low-order filter. An input terminal of the high-order filter is connected to an output terminal of the current-mode PGA unit.

Abstract: A current-mode analog baseband apparatus is provided. The apparatus includes a current-mode low-order filter, a current-mode programmable gain amplifier (PGA) unit and a high-order filter. The input impedance is smaller than the output impedance in the current-mode low-order filter. An input terminal of the current-mode PGA unit is connected to an output terminal of the current-mode low-order filter. An input terminal of the high-order filter is connected to an output terminal of the current-mode PGA unit.

Abstract: A current-mode analog baseband apparatus is provided. The apparatus includes a current-mode low-order filter, a current-mode programmable gain amplifier (PGA) unit and a high-order filter. The input impedance is smaller than the output impedance in the current-mode low-order filter. An input terminal of the current-mode PGA unit is connected to an output terminal of the current-mode low-order filter. An input terminal of the high-order filter is connected to an output terminal of the current-mode PGA unit.