Patents by Inventor Wei-Hsin Liu

Wei-Hsin Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11982866
    Abstract: An optical element driving mechanism is provided and includes a fixed assembly, a movable assembly, a driving assembly and a stopping assembly. The fixed assembly has a main axis. The movable assembly is configured to connect an optical element, and the movable assembly is movable relative to the fixed assembly. The driving assembly is configured to drive the movable assembly to move relative to the fixed assembly. The stopping assembly is configured to limit the movement of the movable assembly relative to the fixed assembly within a range of motion.
    Type: Grant
    Filed: December 15, 2022
    Date of Patent: May 14, 2024
    Assignee: TDK TAIWAN CORP.
    Inventors: Chao-Chang Hu, Liang-Ting Ho, Chen-Er Hsu, Yi-Liang Chan, Fu-Lai Tseng, Fu-Yuan Wu, Chen-Chi Kuo, Ying-Jen Wang, Wei-Han Hsia, Yi-Hsin Tseng, Wen-Chang Lin, Chun-Chia Liao, Shou-Jen Liu, Chao-Chun Chang, Yi-Chieh Lin, Shang-Yu Hsu, Yu-Huai Liao, Shih-Wei Hung, Sin-Hong Lin, Kun-Shih Lin, Yu-Cheng Lin, Wen-Yen Huang, Wei-Jhe Shen, Chih-Shiang Wu, Sin-Jhong Song, Che-Hsiang Chiu, Sheng-Chang Lin
  • Publication number: 20240118522
    Abstract: A photographing lens assembly includes, in order from an object side to an image side: a first, a second, a third, a fourth, a fifth and a sixth lens elements. The first lens element with negative refractive power has an object-side surface being concave in a paraxial region thereof, wherein the object-side surface has at least one convex critical point in an off-axis region thereof. The third lens element has an image-side surface being convex in a paraxial region thereof. The fourth lens element has positive refractive power. The fifth lens element with negative refractive power has an object-side surface being concave in a paraxial region thereof, and an image-side surface being convex in a paraxial region thereof. The sixth lens element has an image-side surface being concave in a paraxial region thereof, wherein the image-side surface has at least one convex critical point in an off-axis region thereof.
    Type: Application
    Filed: December 7, 2023
    Publication date: April 11, 2024
    Applicant: LARGAN PRECISION CO., LTD.
    Inventors: Po-Lun HSU, Wei-Yu CHEN, Kuan-Ting YEH, Ssu-Hsin LIU
  • Patent number: 11953372
    Abstract: An optical sensing device is disclosed. The optical sensing device includes a sensing pixel, a driving circuit and a first light shielding layer. The sensing pixel includes a sensing circuit and a sensing element electrically connected to the sensing circuit. The driving circuit is electrically connected to the sensing circuit. The first light shielding layer includes at least one first opening corresponding to the sensing element, and the first light shielding layer is overlapped with the driving circuit in a top-view direction of the optical sensing device.
    Type: Grant
    Filed: January 18, 2022
    Date of Patent: April 9, 2024
    Assignee: InnoLux Corporation
    Inventors: Yu-Tsung Liu, Wei-Ju Liao, Wei-Lin Wan, Cheng-Hsueh Hsieh, Po-Hsin Lin, Te-Yu Lee
  • Patent number: 11948702
    Abstract: A radiation source apparatus includes a vessel, a laser source, a collector, a horizontal obscuration bar, and a reflective mirror. The vessel has an exit aperture. The laser source is configured to emit a laser beam to excite a target material to form a plasma. The collector is disposed in the vessel and configured to collect a radiation emitted by the plasma and to reflect the collected radiation to the exit aperture of the vessel. The horizontal obscuration bar extends from a sidewall of the vessel at least to a position between the laser source and the exit aperture of the vessel. The reflective mirror is in the vessel and connected to the horizontal obscuration bar.
    Type: Grant
    Filed: May 5, 2023
    Date of Patent: April 2, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Chung Tu, Sheng-Kang Yu, Shang-Chieh Chien, Li-Jui Chen, Heng-Hsin Liu
  • Publication number: 20240081015
    Abstract: An electronic device includes a chassis casing, a device casing, a latch assembly, a bracket, and a rotating shaft assembly. The chassis casing includes a bottom plate. The device casing is detachably disposed in the chassis casing, and the device casing is provided with a stopper. The latch assembly is disposed at the chassis casing, and the latch assembly includes a sliding member. The bracket is disposed in the chassis casing and at an end of the device casing opposite to the latch assembly. The rotating shaft assembly is respectively connected to the device casing and the bracket. The device casing is adjustable between an installation position and an lifting position via the rotating shaft assembly. The sliding member of the latch assembly is used to fix the stopper, so that the device casing is located at the installation position.
    Type: Application
    Filed: November 4, 2022
    Publication date: March 7, 2024
    Inventors: Chia-Hsin Liu, Yu-Jian Wu, Wei Lin
  • Publication number: 20240069416
    Abstract: A light path folding element includes a first surface, a second surface, a first reflecting surface and a second reflecting surface. A light travels from the first surface into the light path folding element. The second surface is disposed relative to the first surface along a first direction and is parallel to the first surface, and the first direction is perpendicular to the first surface. The first reflecting surface connects the first surface and the second surface, an acute angle is formed between the first reflecting surface and the first surface, and the light forms an internal reflection via the first reflecting surface. The light forms another internal reflection via the second reflecting surface. The light path folding element further includes a light blocking structure, which extends from at least one of the first surface and the second surface into the light path folding element.
    Type: Application
    Filed: August 24, 2023
    Publication date: February 29, 2024
    Inventors: Ssu-Hsin LIU, Wei-Che TUNG, Lin-An CHANG, Ming-Ta CHOU
  • Patent number: 11088023
    Abstract: A method of forming a semiconductor structure includes providing a material layer having a recess formed therein. A first tungsten metal layer is formed at a first temperature and fills the recess. An anneal process at a second temperature is then performed, wherein the second temperature is higher than the first temperature.
    Type: Grant
    Filed: March 21, 2018
    Date of Patent: August 10, 2021
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Pin-Hong Chen, Chih-Chieh Tsai, Tzu-Chieh Chen, Kai-Jiun Chang, Chia-Chen Wu, Yi-An Huang, Tsun-Min Cheng, Yi-Wei Chen, Wei-Hsin Liu
  • Patent number: 10903328
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a shallow trench isolation (STI) in the substrate; removing part of the STI to form a trench in a substrate; forming an amorphous silicon layer in the trench and on the STI; performing an oxidation process to transform the amorphous silicon layer into a silicon dioxide layer; and forming a barrier layer and a conductive layer in the trench.
    Type: Grant
    Filed: April 3, 2018
    Date of Patent: January 26, 2021
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Po-Chun Chen, Chia-Lung Chang, Yi-Wei Chen, Wei-Hsin Liu, Han-Yung Tsai
  • Patent number: 10811272
    Abstract: A method of forming a dielectric layer includes the following steps. A substrate including a first area and a second area is provided. A plurality of patterns on the substrate of the first area and a blanket stacked structure on the substrate of the second area are formed. An organic dielectric layer covers the patterns, the blanket stacked structure and the substrate. The blanket stacked structure is patterned by serving the organic dielectric layer as a hard mask layer, thereby forming a plurality of stacked structures. The organic dielectric layer is removed. A dielectric layer blanketly covers the patterns, the stacked structures, and the substrate.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: October 20, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wei-Hsin Liu, Ta-Wei Chiu, Chia-Lung Chang, Po-Chun Chen, Hong-Yi Fang, Yi-Wei Chen
  • Publication number: 20200227269
    Abstract: A method of forming a dielectric layer includes the following steps. A substrate including a first area and a second area is provided. A plurality of patterns on the substrate of the first area and a blanket stacked structure on the substrate of the second area are formed. An organic dielectric layer covers the patterns, the blanket stacked structure and the substrate. The blanket stacked structure is patterned by serving the organic dielectric layer as a hard mask layer, thereby forming a plurality of stacked structures. The organic dielectric layer is removed. A dielectric layer blanketly covers the patterns, the stacked structures, and the substrate.
    Type: Application
    Filed: January 30, 2019
    Publication date: July 16, 2020
    Inventors: Wei-Hsin Liu, Ta-Wei Chiu, Chia-Lung Chang, Po-Chun Chen, Hong-Yi Fang, Yi-Wei Chen
  • Patent number: 10672864
    Abstract: A semiconductor memory device includes a semiconductor substrate, a first support layer, a first electrode, a capacitor dielectric layer, and a second electrode. The first support layer is disposed on the semiconductor substrate. The first electrode is disposed on the semiconductor substrate and penetrates the first support layer. The capacitor dielectric layer is disposed on the first electrode. The second electrode is disposed on the semiconductor substrate, and at least a part of the capacitor dielectric layer is disposed between the first electrode and the second electrode. The first support layer includes a carbon doped nitride layer, and a carbon concentration of a bottom portion of the first support layer is higher than a carbon concentration of a top portion of the first support layer.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: June 2, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Tzu-Chin Wu, Wei-Hsin Liu, Yi-Wei Chen, Chia-Lung Chang, Jui-Min Lee, Po-Chun Chen, Li-Wei Feng, Ying-Chiao Wang, Wen-Chieh Lu, Chien-Ting Ho, Tsung-Ying Tsai, Kai-Ping Chen
  • Patent number: 10643883
    Abstract: A method of forming an isolation structure includes the following steps. A substrate having a first trench, a second trench and a third trench is provided, wherein the opening of the third trench is larger than the opening of the second trench, and the opening of the second trench is larger than the opening of the first trench. A first oxide layer is formed to conformally cover the first trench, the second trench and the third trench by an atomic layer deposition (ALD) process. A second oxide layer fills up the first trench by an in-situ steam generation (ISSG) process.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: May 5, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Po-Chun Chen, Hsuan-Tung Chu, Yi-Wei Chen, Wei-Hsin Liu, Yu-Cheng Tung, Chia-Lung Chang
  • Publication number: 20200075397
    Abstract: A method of forming an isolation structure includes the following steps. A substrate having a first trench, a second trench and a third trench is provided, wherein the opening of the third trench is larger than the opening of the second trench, and the opening of the second trench is larger than the opening of the first trench. A first oxide layer is formed to conformally cover the first trench, the second trench and the third trench by an atomic layer deposition (ALD) process. A second oxide layer fills up the first trench by an in-situ steam generation (ISSG) process.
    Type: Application
    Filed: September 19, 2018
    Publication date: March 5, 2020
    Inventors: Po-Chun Chen, Hsuan-Tung Chu, Yi-Wei Chen, Wei-Hsin Liu, Yu-Cheng Tung, Chia-Lung Chang
  • Patent number: 10535664
    Abstract: A method of changing a formation rate of silicon oxide includes providing a substrate, wherein two conductive lines are disposed on the substrate and a recess is between the conductive lines. Later, a cleaning process is performed to clean the substrate and the conductive lines using diluted hydrofluoric acid. After the cleaning process, a silicon oxide layer is formed to cover a sidewall and a bottom of the recess, wherein a formation rate of the silicon oxide layer at the bottom of the recess is greater than a formation rate of the silicon oxide layer at the sidewall of the recess.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: January 14, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Po-Chun Chen, Wei-Hsin Liu, Chia-Lung Chang, Yi-Wei Chen, Han-Yung Tsai
  • Publication number: 20190363093
    Abstract: A method of changing a formation rate of silicon oxide includes providing a substrate, wherein two conductive lines are disposed on the substrate and a recess is between the conductive lines. Later, a cleaning process is performed to clean the substrate and the conductive lines using diluted hydrofluoric acid. After the cleaning process, a silicon oxide layer is formed to cover a sidewall and a bottom of the recess, wherein a formation rate of the silicon oxide layer at the bottom of the recess is greater than a formation rate of the silicon oxide layer at the sidewall of the recess.
    Type: Application
    Filed: June 19, 2018
    Publication date: November 28, 2019
    Inventors: Po-Chun Chen, Wei-Hsin Liu, Chia-Lung Chang, Yi-Wei Chen, Han-Yung Tsai
  • Patent number: 10475900
    Abstract: A method for manufacturing a semiconductor device with a cobalt silicide film is provided in the present invention. The method includes the steps of providing a silicon structure with an interlayer dielectric formed thereon, forming a contact hole in the interlayer dielectric to expose the silicon structure, depositing a cobalt film on the exposed silicon structure at a temperature between 300° C.-400° C., wherein a cobalt protecting film is in-situ formed on the surface of the cobalt film, performing a rapid thermal process to transform the cobalt film into a cobalt silicide film, and removing untransformed cobalt film.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: November 12, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Kai-Jiun Chang, Tsun-Min Cheng, Chih-Chieh Tsai, Jui-Min Lee, Yi-Wei Chen, Chia-Lung Chang, Wei-Hsin Liu
  • Patent number: 10475662
    Abstract: A method of forming a semiconductor memory device includes following steps. First of all, a target layer is provided, and a mask structure is formed on the target layer, with the mask structure including a first mask layer a sacrificial layer and a second mask layer. The first mask layer and the second mask layer include the same material but in different containing ratio. Next, the second mask layer and the sacrificial layer are patterned, to form a plurality of mandrels. Then, a plurality of spacer patterns are formed to surround the mandrels, and then transferred into the first mask layer to form a plurality of opening not penetrating the first mask layer. Finally, the first mask layer is used as a mask to etch the target layer, to form a plurality of target patterns.
    Type: Grant
    Filed: October 12, 2018
    Date of Patent: November 12, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Wei-Hsin Liu, Ying-Chih Lin, Jui-Min Lee, Gang-Yi Lin, Fu-Che Lee
  • Patent number: 10453677
    Abstract: A method of forming an oxide layer includes the following steps. A substrate is provided. A surface of the substrate is treated to form an oxygen ion-rich surface. A spin-on-dielectric layer is formed on the oxygen ion-rich surface of the substrate. The present invention also provides a method of forming an oxide layer including the following steps. A substrate is provided. A surface of the substrate is treated with a hydrogen peroxide (H2O2) solution or a surface of the substrate is treated with oxygen containing gas, to form an oxygen ion-rich surface. A spin-on-dielectric layer is formed on the oxygen ion-rich surface of the substrate.
    Type: Grant
    Filed: July 9, 2017
    Date of Patent: October 22, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Cheng-Hsu Huang, Jui-Min Lee, Ching-Hsiang Chang, Yi-Wei Chen, Wei-Hsin Liu, Shih-Fang Tzou
  • Publication number: 20190280095
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a shallow trench isolation (STI) in the substrate; removing part of the STI to form a trench in a substrate; forming an amorphous silicon layer in the trench and on the STI; performing an oxidation process to transform the amorphous silicon layer into a silicon dioxide layer; and forming a barrier layer and a conductive layer in the trench.
    Type: Application
    Filed: April 3, 2018
    Publication date: September 12, 2019
    Inventors: Po-Chun Chen, Chia-Lung Chang, Yi-Wei Chen, Wei-Hsin Liu, Han-Yung Tsai
  • Publication number: 20190221571
    Abstract: A semiconductor memory device includes a semiconductor substrate and a patterned conductive structure. The patterned conductive structure is disposed on the semiconductor substrate. The patterned conductive structure includes a first silicon conductive layer, a second silicon conductive layer, an interface layer, a barrier layer, and a metal conductive layer. The second silicon conductive layer is disposed on the first silicon conductive layer. The interface layer is disposed between the first silicon conductive layer and the second silicon conductive layer, and the interface layer includes oxygen. The barrier layer is disposed on the second silicon conductive layer. The metal conductive layer is disposed on the barrier layer.
    Type: Application
    Filed: January 31, 2018
    Publication date: July 18, 2019
    Inventors: Wei-Hsin Liu, Cheng-Hsu Huang, Jui-Min Lee, Yi-Wei Chen