Patents by Inventor Wei-Hsuan Lee
Wei-Hsuan Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240176004Abstract: An electronic device comprises: a radio frequency (RF) front end circuit for generating wireless signals; an antenna array for transmitting the wireless signals generated by the RF front end circuit and receiving the wireless signals transmitted by the antenna array; and a control unit coupled to the RF front end circuit. In the embodiments, a receiving power or a receiving power difference is estimated based on the wireless signals received by the RF front end circuit; and a distance information between an external object and the electronic device is determined based on the receiving power difference, or whether the external object is within a detection area of the electronic device is determined based on the receiving power.Type: ApplicationFiled: November 30, 2022Publication date: May 30, 2024Inventors: Wei-Hsuan CHANG, Cheng-Han LEE, Chih-Wei LEE
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Patent number: 11973260Abstract: A light-transmitting antenna includes a substrate, a first and a second conductive pattern. The first and the second conductive pattern is disposed on a first and a second surface of the substrate respectively. The first conductive pattern includes a first feeder unit, a first and a second radiation unit, a first and a second coupling unit and a first parasitic unit. The first feeder unit is connected to the second radiation unit. The first and the second radiation unit are located between the first and the second coupling unit. One side and the other side of the first parasitic unit is connected to the second coupling unit and adjacent to the first coupling unit respectively. The second conductive pattern includes a second feeder unit, a third coupling unit, a second parasitic unit, and a fourth coupling unit.Type: GrantFiled: November 9, 2022Date of Patent: April 30, 2024Assignee: Industrial Technology Research InstituteInventors: Ruo-Lan Chang, Mei-Ju Lee, Cheng-Hua Tsai, Meng-Hsuan Chen, Wei-Chung Chen
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Publication number: 20240120656Abstract: A light-transmitting antenna includes a substrate, a first conductive pattern, and a second conductive pattern. The first conductive pattern has a first feeder unit, a first radiation unit, a second radiation unit, and a first connection unit. The first feeder unit and the first connection unit are connected to two sides of the first radiation unit. The first connection unit connects the first radiation unit and the second radiation unit. The second conductive pattern has a second feeder unit, a third radiation unit, a fourth radiation unit, and a second connection unit. The second feeder unit and the second connection unit are connected to two sides of the third radiation unit. The second connection unit connects the third radiation unit and the fourth radiation unit. An orthogonal projection of the second feeder unit on a first surface of the substrate at least partially overlaps the first feeder unit.Type: ApplicationFiled: December 22, 2022Publication date: April 11, 2024Applicant: Industrial Technology Research InstituteInventors: Meng-Hsuan Chen, Cheng-Hua Tsai, Mei-Ju Lee, Ruo-Lan Chang, Wei-Chung Chen
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Publication number: 20240113202Abstract: Embodiments of the present disclosure relate to a FinFET device having gate spacers with reduced capacitance and methods for forming the FinFET device. Particularly, the FinFET device according to the present disclosure includes gate spacers formed by two or more depositions. The gate spacers are formed by depositing first and second materials at different times of processing to reduce parasitic capacitance between gate structures and contacts introduced after epitaxy growth of source/drain regions.Type: ApplicationFiled: December 1, 2023Publication date: April 4, 2024Inventors: Wen-Kai Lin, Bo-Yu Lai, Li Chun Te, Kai-Hsuan Lee, Sai-Hooi Yeong, Tien-I Bao, Wei-Ken Lin
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Publication number: 20240088155Abstract: A semiconductor device includes source/drain regions, a gate structure, a first gate spacer, and a dielectric material. The source/drain regions are over a substrate. The gate structure is laterally between the source/drain regions. The first gate spacer is on a first sidewall of the gate structure, and spaced apart from a first one of the source/drain regions at least in part by a void region. The dielectric material is between the first one of the source/drain regions and the void region. The dielectric material has a gradient ratio of a first chemical element to a second chemical element.Type: ApplicationFiled: November 15, 2023Publication date: March 14, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Bo-Yu LAI, Kai-Hsuan LEE, Wei-Yang LEE, Feng-Cheng YANG, Yen-Ming CHEN
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Patent number: 11152274Abstract: A semiconductor device package includes a semiconductor device, a conductive bump, a first encapsulant and a second encapsulant. The semiconductor device has a first surface, a second surface and a lateral surface. The second surface is opposite to the first surface. The lateral surface extends between the first surface and the second surface. The semiconductor device comprises a conductive pad adjacent to the first surface of the semiconductor device. The conductive bump is electrically connected to the conductive pad. The first encapsulant covers the first surface of the semiconductor device and a first portion of the lateral surface of the semiconductor device, and surrounds the conductive bump. The second encapsulant covers the second surface of the semiconductor device and a second portion of the lateral surface of the semiconductor device.Type: GrantFiled: September 11, 2017Date of Patent: October 19, 2021Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Wei-Hsuan Lee, Sung-Mao Li, Ming-Han Wang, Ian Hu
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Patent number: 10756025Abstract: A semiconductor package device includes: (1) a substrate having a top surface; (2) a passive component disposed on the substrate and having a top surface; (3) an active component disposed on the substrate and having a top surface; and (4) a package body disposed on the substrate, the package body including a first portion covering the active component and the passive component, and a second portion covering the passive component, wherein a top surface of the second portion of the package body is higher than a top surface of the first portion of the package body, and the first portion and the second portion of the package body include different materials.Type: GrantFiled: August 8, 2018Date of Patent: August 25, 2020Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Wei-Hsuan Lee, Jaw-Ming Ding, Wei-Yu Chen
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Publication number: 20190080975Abstract: A semiconductor device package includes a semiconductor device, a conductive bump, a first encapsulant and a second encapsulant. The semiconductor device has a first surface, a second surface and a lateral surface. The second surface is opposite to the first surface. The lateral surface extends between the first surface and the second surface. The semiconductor device comprises a conductive pad adjacent to the first surface of the semiconductor device. The conductive bump is electrically connected to the conductive pad. The first encapsulant covers the first surface of the semiconductor device and a first portion of the lateral surface of the semiconductor device, and surrounds the conductive bump. The second encapsulant covers the second surface of the semiconductor device and a second portion of the lateral surface of the semiconductor device.Type: ApplicationFiled: September 11, 2017Publication date: March 14, 2019Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Wei-Hsuan LEE, Sung-Mao LI, Ming-Han WANG, Ian HU
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Patent number: 10157855Abstract: The present disclosure relates to a semiconductor device package and a manufacturing method thereof. The semiconductor device package includes a carrier, at least one electronic component, a first magnetic layer and a second magnetic layer. The carrier has a top surface on which the electronic component is disposed. The first magnetic layer is disposed on the top surface of the carrier and encapsulates the electronic component. The second magnetic layer is disposed on the first magnetic layer and covers a top surface and a lateral surface of the first magnetic layer. A permeability of the first magnetic layer is less than a permeability of the second magnetic layer.Type: GrantFiled: June 3, 2015Date of Patent: December 18, 2018Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Wei-Hsuan Lee, Chien-Yeh Liu, Sung-Mao Li, Jaw-Ming Ding
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Publication number: 20180350753Abstract: A semiconductor package device includes: (1) a substrate having a top surface; (2) a passive component disposed on the substrate and having a top surface; (3) an active component disposed on the substrate and having a top surface; and (4) a package body disposed on the substrate, the package body including a first portion covering the active component and the passive component, and a second portion covering the passive component, wherein a top surface of the second portion of the package body is higher than a top surface of the first portion of the package body, and the first portion and the second portion of the package body include different materials.Type: ApplicationFiled: August 8, 2018Publication date: December 6, 2018Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Wei-Hsuan LEE, Jaw-Ming Ding, Wei-Yu CHEN
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Patent number: 10068854Abstract: A semiconductor package device includes a substrate, a passive component, an active component and a package body. The passive component is disposed on the substrate. The active component is disposed on the substrate. The package body is disposed on the substrate. The package body includes a first portion covering the active component and the passive component, and a second portion covering the passive component. A top surface of the second portion of the package body is higher than a top surface of the first portion of the package body.Type: GrantFiled: October 24, 2016Date of Patent: September 4, 2018Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Wei-Hsuan Lee, Jaw-Ming Ding, Wei-Yu Chen
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Publication number: 20180114757Abstract: A semiconductor package device includes a substrate, a passive component, an active component and a package body. The passive component is disposed on the substrate. The active component is disposed on the substrate. The package body is disposed on the substrate. The package body includes a first portion covering the active component and the passive component, and a second portion covering the passive component. A top surface of the second portion of the package body is higher than a top surface of the first portion of the package body.Type: ApplicationFiled: October 24, 2016Publication date: April 26, 2018Inventors: Wei-Hsuan LEE, Jaw-Ming DING, Wei-Yu CHEN
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Publication number: 20180114758Abstract: A semiconductor device package comprises a substrate, a first electronic component, first and second conductive pads, a first frame board, an encapsulation layer, and a conductive layer. The substrate has a first surface and a second surface opposite to the first surface. The first electronic component, the first and second conductive pads, and the first frame board are on the first surface of the substrate. The first frame board surrounds the first electronic component and comprises a first conductive via and a second electronic component. The encapsulation layer encapsulates the first electronic component and the first frame board. The conductive layer is on the first frame board and the encapsulation layer. The first conductive via is electrically connected to the second conductive pad and the conductive layer, and the second electronic component is electrically connected to the first conductive pad.Type: ApplicationFiled: October 25, 2016Publication date: April 26, 2018Inventors: Chih Sheng YAO, Huan Wun LI, Yu-Chih LEE, Wei-Hsuan LEE
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Patent number: 9953931Abstract: A semiconductor device package comprises a substrate, a first electronic component, first and second conductive pads, a first frame board, an encapsulation layer, and a conductive layer. The substrate has a first surface and a second surface opposite to the first surface. The first electronic component, the first and second conductive pads, and the first frame board are on the first surface of the substrate. The first frame board surrounds the first electronic component and comprises a first conductive via and a second electronic component. The encapsulation layer encapsulates the first electronic component and the first frame board. The conductive layer is on the first frame board and the encapsulation layer. The first conductive via is electrically connected to the second conductive pad and the conductive layer, and the second electronic component is electrically connected to the first conductive pad.Type: GrantFiled: October 25, 2016Date of Patent: April 24, 2018Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INCInventors: Chih Sheng Yao, Huan Wun Li, Yu-Chih Lee, Wei-Hsuan Lee
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Patent number: 9653415Abstract: The present disclosure relates to a semiconductor device package. The semiconductor device package includes a substrate, a semiconductor device, a plurality of electronic components, a first package body, a patterned conductive layer and a feeding element. The semiconductor device and the plurality of electronic components are disposed on the substrate. The first package body covers the semiconductor device but exposes the plurality of electronic components. The patterned conductive layer is formed on the first package body. The feeding element electrically connects the patterned conductive layer to the plurality of electronic components.Type: GrantFiled: February 18, 2015Date of Patent: May 16, 2017Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Wei-Hsuan Lee, Sung-Mao Li, Chien-Yeh Liu
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Publication number: 20160358862Abstract: The present disclosure relates to a semiconductor device package and a manufacturing method thereof. The semiconductor device package includes a carrier, at least one electronic component, a first magnetic layer and a second magnetic layer. The carrier has a top surface on which the electronic component is disposed. The first magnetic layer is disposed on the top surface of the carrier and encapsulates the electronic component. The second magnetic layer is disposed on the first magnetic layer and covers a top surface and a lateral surface of the first magnetic layer. A permeability of the first magnetic layer is less than a permeability of the second magnetic layer.Type: ApplicationFiled: June 3, 2015Publication date: December 8, 2016Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Wei-Hsuan Lee, Chien-Yeh Liu, Sung-Mao Li, Jaw-Ming Ding
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Publication number: 20160240493Abstract: The present disclosure relates to a semiconductor device package. The semiconductor device package includes a substrate, a semiconductor device, a plurality of electronic components, a first package body, a patterned conductive layer and a feeding element. The semiconductor device and the plurality of electronic components are disposed on the substrate. The first package body covers the semiconductor device but exposes the plurality of electronic components. The patterned conductive layer is formed on the first package body. The feeding element electrically connects the patterned conductive layer to the plurality of electronic components.Type: ApplicationFiled: February 18, 2015Publication date: August 18, 2016Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Wei-Hsuan LEE, Sung-Mao LI, Chien-Yeh LIU
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Patent number: 9397074Abstract: A semiconductor package includes a substrate, a set of electrical components, a stud, a tapering electrical interconnection and a package body. The electrical components are disposed on a top surface of the substrate. A bottom surface of the stud is disposed on the top surface of the substrate. A bottom surface of the electrical interconnection is disposed at a top surface of the stud. A width of the stud is greater than or equal to a width of the bottom surface of the electrical interconnection. The package body is disposed on the top surface of the substrate, and encapsulates the electrical components, the stud and a portion of the electrical interconnection. The package body exposes a top surface of the electrical interconnection.Type: GrantFiled: April 29, 2015Date of Patent: July 19, 2016Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Wei-Hsuan Lee, Sung-Mao Li, Chien-Yeh Liu
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Patent number: 9123981Abstract: A tunable radio frequency (RF) coupler and manufacturing method thereof are provided. The tunable RF coupler includes an insulating layer, a first transmission line and a second transmission line. The second transmission line is disposed corresponding to the first transmission line and the insulating layer is disposed between the first transmission line and the second transmission line. The second transmission line includes a plurality of segments separated from each other and arranged along the extension path of the first transmission line. At least one wire is configured to establish an electrical connection between at least two segments, such that the two segments are electrically conductive to each other through the wire.Type: GrantFiled: April 30, 2014Date of Patent: September 1, 2015Assignee: Advanced Semiconductor Engineering Inc.Inventors: Chien-Yeh Liu, Wei-Hsuan Lee, Jaw-Ming Ding, Huang-Hua Wen
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Publication number: 20150244053Abstract: A tunable radio frequency (RF) coupler and manufacturing method thereof are provided. The tunable RF coupler includes an insulating layer, a first transmission line and a second transmission line. The second transmission line is disposed corresponding to the first transmission line and the insulating layer is disposed between the first transmission line and the second transmission line. The second transmission line includes a plurality of segments separated from each other and arranged along the extension path of the first transmission line. At least one wire is configured to establish an electrical connection between at least two segments, such that the two segments are electrically conductive to each other through the wire.Type: ApplicationFiled: April 30, 2014Publication date: August 27, 2015Applicant: ADVANCED SEMICONDUCTOR ENGINEERING INC.Inventors: CHIEN-YEH LIU, Wei-Hsuan Lee, JAW-MING DING, Huang-Hua Wen