Patents by Inventor Wei-Hung Lin

Wei-Hung Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230138244
    Abstract: An example approach to detect inputs using a sensor is disclosed. In an example, an electronic device may include a housing, an optical sensor to detect an input from a detection zone, and a rotatable housing mounted to a side of the housing. The optical sensor is disposed in the rotatable housing. The electronic device may also include a direction sensor to detect an orientation of the rotatable housing relative to the housing.
    Type: Application
    Filed: April 7, 2020
    Publication date: May 4, 2023
    Applicant: Hewlett-Packard Development Company, L.P.
    Inventors: Wei Hung Lin, Hung Sung Pan, Simon Wong
  • Patent number: 11640954
    Abstract: A semiconductor package structure includes a plurality of first dies spaced from each other, a molding layer between the first dies, a second die over the plurality of first dies and the molding layer, and an adhesive layer between the plurality of first dies and the second die, and between the molding layer and the second die. A first interface between the adhesive layer and the molding layer and a second interface between the adhesive layer and the plurality of first dies are at different levels.
    Type: Grant
    Filed: March 31, 2021
    Date of Patent: May 2, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Jeng-Nan Hung, Chun-Hui Yu, Kuo-Chung Yee, Yi-Da Tsai, Wei-Hung Lin, Ming-Da Cheng, Ching-Hua Hsieh
  • Publication number: 20230098830
    Abstract: Package structures and methods for forming the same are provided. The method includes forming a passivation layer having an opening and forming a first seed layer in the opening. The method further includes filling the opening with a conductive layer over the first seed layer and bonding an integrated circuit die to the conductive layer over a first side of the passivation layer. The method further includes removing a portion of the first seed layer to expose a top surface of the conductive layer and to partially expose a first sidewall of the passivation layer from a second side of the passivation layer and forming a second seed layer over the top surface of the conductive layer and over the first sidewall of the passivation layer.
    Type: Application
    Filed: December 8, 2022
    Publication date: March 30, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi-Da TSAI, Cheng-Ping LIN, Wei-Hung LIN, Chih-Wei LIN, Ming-Da CHENG, Ching-Hua HSIEH, Chung-Shi LIU
  • Publication number: 20230077550
    Abstract: In some examples, an electronic device includes a tip pressure sensor to capture tip pressure data based on a writing surface. In some examples, the electronic device includes a processor to produce a classification of the writing surface based on the tip pressure data via a machine learning model. In some examples, the electronic device may include a haptic device to control haptic feedback based on the classification.
    Type: Application
    Filed: September 15, 2021
    Publication date: March 16, 2023
    Inventors: Tai Hsiang Chen, Charles J. Stancil, Wei-Hung Lin, Kun-Hung Lin
  • Publication number: 20230062370
    Abstract: Provided are a package structure and a method of forming the same. The method includes providing a first package having a plurality of first dies and a plurality of second dies therein; performing a first sawing process to cut the first package into a plurality of second packages, wherein one of the plurality of second packages comprises three first dies and one second die; and performing a second sawing process to remove the second die of the one of the plurality of second packages, so that a cut second package is formed into a polygonal structure with the number of nodes greater than or equal to 5.
    Type: Application
    Filed: August 30, 2021
    Publication date: March 2, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Hung Lin, Hui-Min Huang, Chang-Jung Hsueh, Wan-Yu Chiang, Ming-Da Cheng, Mirng-Ji Lii
  • Publication number: 20230065797
    Abstract: A semiconductor die including mechanical-stress-resistant bump structures is provided. The semiconductor die includes dielectric material layers embedding metal interconnect structures, a connection pad-and-via structure, and a bump structure including a bump via portion and a bonding bump portion. The entirety of a bottom surface of the bump via portion is located within an area of a horizontal top surface of a pad portion of the connection pad-and-via structure.
    Type: Application
    Filed: August 26, 2021
    Publication date: March 2, 2023
    Inventors: Hui-Min HUANG, Ming-Da CHENG, Chang-Jung HSUEH, Wei-Hung LIN, Kai Jun ZHAN, Wan-Yu CHIANG
  • Publication number: 20230062138
    Abstract: A semiconductor package structure includes first via structures formed through a core substrate. The structure also includes an interposer embedded in the core substrate between the first via structures. The interposer includes second via structures formed through an interposer substrate. The structure also includes a first redistribution layer structure formed over the core substrate. The structure also includes a second redistribution layer structure formed under the core substrate. The structure also includes a first encapsulating layer formed between a sidewall of the interposer and a sidewall of the core substrate.
    Type: Application
    Filed: August 30, 2021
    Publication date: March 2, 2023
    Inventors: Po-Hao TSAI, Wei-Hung LIN, Ming-Da CHENG, Mirng-Ji LII
  • Publication number: 20230065147
    Abstract: A semiconductor package includes a substrate, a semiconductor die, a lid, and an adhesive layer. The semiconductor die is attached to the substrate. The lid is over the semiconductor die and the substrate. The adhesive layer is sandwiched between the lid and the semiconductor die. The adhesive layer includes a metallic thermal interface material (TIM) layer and a polymeric TIM layer adjacent to the metallic TIM layer. The polymeric TIM layer is located on corners of the semiconductor die from a top view.
    Type: Application
    Filed: August 30, 2021
    Publication date: March 2, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuan-Min Wang, Chang-Jung Hsueh, Jui-Chang Chuang, Wei-Hung Lin, Kuo-Chin Chang
  • Publication number: 20230063127
    Abstract: A structure and a formation method of a semiconductor device are provided. The semiconductor device structure includes a semiconductor substrate and an interconnection structure over the semiconductor substrate. The semiconductor device structure also includes a first conductive pillar over the interconnection structure. The first conductive pillar has a first protruding portion extending towards the semiconductor substrate from a lower surface of the first conductive pillar. The semiconductor device structure further includes a second conductive pillar over the interconnection structure. The second conductive pillar has a second protruding portion extending towards the semiconductor substrate from a lower surface of the second conductive pillar. The first conductive pillar is closer to a center point of the semiconductor substrate than the second conductive pillar. A bottom of the second protruding portion is wider than a bottom of the first protruding portion.
    Type: Application
    Filed: August 27, 2021
    Publication date: March 2, 2023
    Inventors: Hui-Min HUANG, Ming-Da CHENG, Wei-Hung LIN, Chang-Jung HSUEH, Kai-Jun ZHAN, Yung-Sheng LIN
  • Publication number: 20230068485
    Abstract: A semiconductor device includes a substrate, an interconnect structure, and conductive vias. The substrate has a first side, a second side and a sidewall connecting the first side and the second side, wherein the sidewall includes a first planar sidewall of a first portion of the substrate, a second planar sidewall of a second portion of the substrate and a curved sidewall of a third portion of the substrate, where the first planar sidewall is connected to the second planar sidewall through the curved sidewall. The interconnect structure is located on the first side of the substrate, where a sidewall of the interconnect structure is offset from the second planar sidewall. The conductive vias are located on the interconnect structure, where the interconnect structure is located between the conductive vias and the substrate.
    Type: Application
    Filed: August 31, 2021
    Publication date: March 2, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chang-Jung Hsueh, Cheng-Nan Lin, Wan-Yu Chiang, Wei-Hung Lin, Ching-Wen Hsiao, Ming-Da Cheng
  • Publication number: 20230065724
    Abstract: A structure and a formation method of a semiconductor device are provided. The semiconductor device structure includes an interconnection structure over a semiconductor substrate. The semiconductor device structure includes a conductive pillar over the interconnection structure. The conductive pillar has a protruding portion extending towards the semiconductor substrate. The semiconductor device structure includes an upper conductive via between the conductive pillar and the interconnection structure. A center of the upper conductive via is laterally separated from a center of the protruding portion by a first distance. The semiconductor device structure includes a lower conductive via between the upper conductive via and the interconnection structure. The lower conductive via is electrically connected to the conductive pillar through the upper conductive via.
    Type: Application
    Filed: August 27, 2021
    Publication date: March 2, 2023
    Inventors: Ming-Da Cheng, Wei-Hung Lin, Hui-Min Huang, Chang-Jung Hsueh, Po-Hao Tsai, Yung-Sheng Lin
  • Publication number: 20230067143
    Abstract: A chip structure is provided. The chip structure includes a substrate. The chip structure includes a first conductive line over the substrate. The chip structure includes an insulating layer over the substrate and the first conductive line. The chip structure includes a conductive pillar over the insulating layer. The conductive pillar is formed in one piece, the conductive pillar has a lower surface, a protruding connecting portion, and a protruding locking portion, the protruding connecting portion protrudes from the lower surface and passes through the insulating layer and is in direct contact with the first conductive line, the protruding locking portion protrudes from the lower surface and is embedded in the insulating layer. The chip structure includes a solder bump on the conductive pillar. The solder bump is in direct contact with the conductive pillar.
    Type: Application
    Filed: August 30, 2021
    Publication date: March 2, 2023
    Inventors: Hui-Min HUANG, Ming-Da CHENG, Wei-Hung LIN, Chang-Jung HSUEH, Kai-Jun ZHAN, Yung-Sheng LIN
  • Patent number: 11532564
    Abstract: Package structures and methods for forming the same are provided. The package structure includes an integrated circuit die and a package layer surrounding the integrated circuit die. The package structure also includes a redistribution structure over the package layer and electrically connected to the integrated circuit die. The redistribution structure includes a passivation layer and a conductive layer formed in the passivation layer. The integrated circuit die further includes a connector formed over the conductive layer and covered a top surface of the passivation layer. In addition, a bottom surface of the connector and a top surface of the connector are both wider than a neck portion of the connector.
    Type: Grant
    Filed: December 14, 2020
    Date of Patent: December 20, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Da Tsai, Cheng-Ping Lin, Wei-Hung Lin, Chih-Wei Lin, Ming-Da Cheng, Ching-Hua Hsieh, Chung-Shi Liu
  • Publication number: 20220384287
    Abstract: A method includes forming a reconstructed package substrate, which includes placing a plurality of substrate blocks over a carrier, encapsulating the plurality of substrate blocks in an encapsulant, planarizing the encapsulant and the plurality of substrate blocks to reveal redistribution lines in the plurality of substrate blocks, and forming a redistribution structure overlapping both of the plurality of substrate blocks and encapsulant. A package component is bonded over the reconstructed package substrate.
    Type: Application
    Filed: August 10, 2022
    Publication date: December 1, 2022
    Inventors: Chen-Shien Chen, Kuo-Ching Hsu, Wei-Hung Lin, Hui-Min Huang, Ming-Da Cheng, Mirng-Ji Lii
  • Patent number: 11474623
    Abstract: An example stylus pen may include a main body including a first battery and a writing tip attached to the main body. Further, the stylus pen may include a cap removably disposed on the main body to cover the writing tip. The cap may include a second battery. Furthermore, the stylus pen may include a controller to charge the first battery from the second battery.
    Type: Grant
    Filed: June 11, 2021
    Date of Patent: October 18, 2022
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Tai Hsiang Chen, Wei Hung Lin, Hung Sung Pan
  • Patent number: 11465017
    Abstract: A luminous safety ball including an inner glowing body and a foam sphere covering the inner glowing body is provided. The inner glowing body is not a perfect sphere, the foam sphere has a non-uniform thickness, and light emitted by the inner glowing body passes through the foam sphere and permeates through a surface of the foam sphere to form light with different brightness thereon.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: October 11, 2022
    Assignee: BLACKSTAR CORP.
    Inventor: Wei-Hung Lin
  • Publication number: 20220283641
    Abstract: In one example, an electronic device may include a touch panel defining an input surface having an input region and a display panel disposed below the touch panel. The display panel may visualize a virtual keyboard including a set of virtual keys. Further, the electronic device may include a haptic array module disposed below the display panel. The haptic array module may include a first actuator disposed below the input region corresponding to a first virtual key of the set of virtual keys. Further, the electronic device may include a controller in communication with the haptic array module to trigger the first actuator to generate a haptic output at the input region in response to an activation of the virtual keyboard.
    Type: Application
    Filed: November 8, 2019
    Publication date: September 8, 2022
    Applicant: Hewlett-Packard Development Company, L.P.
    Inventors: Hung-Ming Chen, Charles Stancil, Tai Hsiang Chen, Wei Hung Lin
  • Publication number: 20220278071
    Abstract: An apparatus for forming a package structure is provided. The apparatus includes a processing chamber for bonding a first package component and a second package component. The apparatus also includes a bonding head disposed in the processing chamber. The bonding head includes a plurality of vacuum tubes communicating with a plurality of vacuum devices. The apparatus further includes a nozzle connected to the bonding head and configured to hold the second package component. The nozzle includes a plurality of first holes that overlap the vacuum tubes. The nozzle also includes a plurality of second holes offset from the first holes, wherein the second holes overlap at least two edges of the second package component. In addition, the apparatus includes a chuck table disposed in the processing chamber, and the chuck table is configured to hold and heat the first package component.
    Type: Application
    Filed: July 8, 2021
    Publication date: September 1, 2022
    Inventors: Kai Jun ZHAN, Chang-Jung HSUEH, Hui-Min HUANG, Wei-Hung LIN, Ming-Da CHENG
  • Publication number: 20220262694
    Abstract: A method includes forming a reconstructed package substrate, which includes placing a plurality of substrate blocks over a carrier, encapsulating the plurality of substrate blocks in an encapsulant, planarizing the encapsulant and the plurality of substrate blocks to reveal redistribution lines in the plurality of substrate blocks, and forming a redistribution structure overlapping both of the plurality of substrate blocks and encapsulant. A package component is bonded over the reconstructed package substrate.
    Type: Application
    Filed: May 12, 2021
    Publication date: August 18, 2022
    Inventors: Chen-Shien Chen, Kuo-Ching Hsu, Wei-Hung Lin, Hui-Min Huang, Ming-Da Cheng, Mirng-Ji Lii
  • Publication number: 20220246435
    Abstract: A method of manufacturing a semiconductor structure includes receiving a die comprising a top surface and a sacrificial layer covering the top surface; disposing a molding surrounding the die; removing the sacrificial layer from the die; disposing a polymer over the die and the molding, wherein the polymer has a first bottom surface contacting the die and a second bottom surface contacting the molding, and the first bottom surface is at a level substantially same as the second bottom surface.
    Type: Application
    Filed: April 22, 2022
    Publication date: August 4, 2022
    Inventors: YU-HSIANG HU, WEI-YU CHEN, HUNG-JUI KUO, WEI-HUNG LIN, MING-DA CHENG, CHUNG-SHI LIU