Patents by Inventor Wei-Jen Huang

Wei-Jen Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11982866
    Abstract: An optical element driving mechanism is provided and includes a fixed assembly, a movable assembly, a driving assembly and a stopping assembly. The fixed assembly has a main axis. The movable assembly is configured to connect an optical element, and the movable assembly is movable relative to the fixed assembly. The driving assembly is configured to drive the movable assembly to move relative to the fixed assembly. The stopping assembly is configured to limit the movement of the movable assembly relative to the fixed assembly within a range of motion.
    Type: Grant
    Filed: December 15, 2022
    Date of Patent: May 14, 2024
    Assignee: TDK TAIWAN CORP.
    Inventors: Chao-Chang Hu, Liang-Ting Ho, Chen-Er Hsu, Yi-Liang Chan, Fu-Lai Tseng, Fu-Yuan Wu, Chen-Chi Kuo, Ying-Jen Wang, Wei-Han Hsia, Yi-Hsin Tseng, Wen-Chang Lin, Chun-Chia Liao, Shou-Jen Liu, Chao-Chun Chang, Yi-Chieh Lin, Shang-Yu Hsu, Yu-Huai Liao, Shih-Wei Hung, Sin-Hong Lin, Kun-Shih Lin, Yu-Cheng Lin, Wen-Yen Huang, Wei-Jhe Shen, Chih-Shiang Wu, Sin-Jhong Song, Che-Hsiang Chiu, Sheng-Chang Lin
  • Publication number: 20240153895
    Abstract: Semiconductor dies of a semiconductor die package are directly bonded, and a top metal region may be formed over the semiconductor dies. A plurality of conductive terminals may be formed over the top metal region. The conductive terminals are formed of copper (Cu) or another material that enables low-temperature deposition process techniques, such as electroplating, to be used to form the conductive terminal. In this way, the conductive terminals of the semiconductor die packages described herein may be formed at a relatively low temperature. This reduces the likelihood of thermal deformation of semiconductor dies in the semiconductor die packages. The reduced thermal deformation reduces the likelihood of warpage, breakage, and/or other types of damage to the semiconductor dies of the semiconductor die packages, which may increase performance and/or increase yield of semiconductor die packages.
    Type: Application
    Filed: April 19, 2023
    Publication date: May 9, 2024
    Inventors: Harry-HakLay CHUANG, Wei-Cheng WU, Chung-Jen HUANG, Yung Chun TU, Chien Lin LIU, Shun-Kuan LIN, Ping-tzu CHEN
  • Publication number: 20240145255
    Abstract: An electronic includes an electronic element, an encapsulation layer surrounding the electronic element, a first circuit structure, a second circuit structure and a connecting structure. The encapsulation layer has a top surface, a bottom surface and an opening, wherein a sidewall of the opening connects the top surface and the bottom surface. The first circuit structure is disposed at the top surface of the encapsulation layer. The second circuit structure is disposed at the bottom surface of the encapsulation layer. The connecting structure is disposed in the opening, wherein the electronic element is electrically connected to the second circuit structure through the first circuit structure and the connecting structure. The connecting structure includes a first sub layer and a second sub layer, the first sub layer is located between the encapsulation layer and the second sub layer, and the first sub layer covers the sidewall of the opening.
    Type: Application
    Filed: September 14, 2023
    Publication date: May 2, 2024
    Applicant: InnoLux Corporation
    Inventors: Ker-Yih KAO, Chin-Ming HUANG, Wei-Yuan CHENG, Jui-Jen YUEH, Kuan-Feng LEE
  • Publication number: 20240136346
    Abstract: A semiconductor die package includes an inductor-capacitor (LC) semiconductor die that is directly bonded with a logic semiconductor die. The LC semiconductor die includes inductors and capacitors that are integrated into a single die. The inductors and capacitors of the LC semiconductor die may be electrically connected with transistors and other logic components on the logic semiconductor die to form a voltage regulator circuit of the semiconductor die package. The integration of passive components (e.g., the inductors and capacitors) of the voltage regulator circuit into a single semiconductor die reduces signal propagation distances in the voltage regulator circuit, which may increase the operating efficiency of the voltage regulator circuit, may reduce the formfactor for the semiconductor die package, may reduce parasitic capacitance and/or may reduce parasitic inductance in the voltage regulator circuit (thereby improving the performance of the voltage regulator circuit), among other examples.
    Type: Application
    Filed: April 17, 2023
    Publication date: April 25, 2024
    Inventors: Chien Hung LIU, Yu-Sheng CHEN, Yi Ching ONG, Hsien Jung CHEN, Kuen-Yi CHEN, Kuo-Ching HUANG, Harry-HakLay CHUANG, Wei-Cheng WU, Yu-Jen WANG
  • Patent number: 11968038
    Abstract: Disclosed are systems, methods, and non-transitory computer-readable storage media for monitoring application health via correctable errors. The method includes identifying, by a network device, a network packet associated with an application and detecting an error associated with the network packet. In response to detecting the error, the network device increments a counter associated with the application, determines an application score based at least in part on the counter, and telemeters the application score to a controller. The controller can generate a graphical interface based at least in part on the application score and a timestamp associated with the application score, wherein the graphical interface depicts a trend in correctable errors experienced by the application over a network.
    Type: Grant
    Filed: July 19, 2021
    Date of Patent: April 23, 2024
    Assignee: Cisco Technology, Inc.
    Inventors: Keerthi Manjunathan Swarnamanjunathan, Chih-Tsung Huang, Kelvin Chan, Wei-Jen Huang
  • Publication number: 20240106737
    Abstract: The present technology is directed to a system and method for application aware management and recovery of link failures resulting from excessive errors observed on the link. One aspect of the proposed technology is based on identification of link errors associated with application-specific data patterns traversing link. Other aspects involve corrective actions based on relocation or modification of specific application traffic to thereby alleviate the observed excessive link errors and prevent a link failure or shut down. Relocation may involve moving the source application to a different virtual machine/container/physical device or rerouting application traffic by updating relevant routing protocols. Modification may involve harmlessly changing payload data pattern to remove data-pattern dependent signal attenuation.
    Type: Application
    Filed: December 7, 2023
    Publication date: March 28, 2024
    Inventors: Chih-Tsung Huang, Wei-Jen Huang
  • Patent number: 11942464
    Abstract: In an embodiment, a method includes: aligning a first package component with a second package component, the first package component having a first region and a second region, the first region including a first conductive connector, the second region including a second conductive connector; performing a first laser shot on a first portion of a top surface of the first package component, the first laser shot reflowing the first conductive connector of the first region, the first portion of the top surface of the first package component completely overlapping the first region; and after performing the first laser shot, performing a second laser shot on a second portion of the top surface of the first package component, the second laser shot reflowing the second conductive connector of the second region, the second portion of the top surface of the first package component completely overlapping the second region.
    Type: Grant
    Filed: July 19, 2021
    Date of Patent: March 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao-Jan Pei, Hsiu-Jen Lin, Wei-Yu Chen, Philip Yu-Shuan Chung, Chia-Shen Cheng, Kuei-Wei Huang, Ching-Hua Hsieh, Chung-Shi Liu, Chen-Hua Yu
  • Publication number: 20240088026
    Abstract: A semiconductor device according to embodiments of the present disclosure includes a first die including a first bonding layer and a second die including a second hybrid bonding layer. The first bonding layer includes a first dielectric layer and a first metal coil embedded in the first dielectric layer. The second bonding layer includes a second dielectric layer and a second metal coil embedded in the second dielectric layer. The second hybrid bonding layer is bonded to the first hybrid bonding layer such that the first dielectric layer is bonded to the second dielectric layer and the first metal coil is bonded to the second metal coil.
    Type: Application
    Filed: January 17, 2023
    Publication date: March 14, 2024
    Inventors: Yi Ching Ong, Wei-Cheng Wu, Chien Hung Liu, Harry-Haklay Chuang, Yu-Sheng Chen, Yu-Jen Wang, Kuo-Ching Huang
  • Publication number: 20240079524
    Abstract: A semiconductor device comprises a first semiconductor structure, a second semiconductor structure located on the first semiconductor structure, and an active layer located between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure has a first conductivity type, and includes a plurality of first layers and a plurality of second layers alternately stacked. The second semiconductor structure has a second conductivity type opposite to the first conductivity type. The plurality of first layers and the plurality of second layers include indium and phosphorus, and the plurality of first layers and the plurality of second layers respectively have a first indium atomic percentage and a second indium atomic percentage. The second indium atomic percentage is different from the first indium atomic percentage.
    Type: Application
    Filed: September 6, 2023
    Publication date: March 7, 2024
    Inventors: Wei-Jen HSUEH, Shih-Chang LEE, Kuo-Feng HUANG, Wen-Luh LIAO, Jiong-Chaso SU, Yi-Chieh LIN, Hsuan-Le LIN
  • Publication number: 20240071911
    Abstract: A semiconductor device includes a first die having a first bonding layer; a second die having a second bonding layer disposed over and bonded to the first bonding layer; a plurality of bonding members, wherein each of the plurality of bonding members extends within the first bonding layer and the second bonding layer, wherein the plurality of bonding members includes a connecting member electrically connected to a first conductive pattern in the first die and a second conductive pattern in the second die, and a dummy member electrically isolated from the first conductive pattern and the second conductive pattern; and an inductor disposed within the first bonding layer and the second bonding layer. A method of manufacturing a semiconductor device includes bonding a first inductive coil of a first die to a second inductive coil of a second die to form an inductor.
    Type: Application
    Filed: January 31, 2023
    Publication date: February 29, 2024
    Inventors: Harry-Haklay Chuang, Wen-Tuo Huang, Li-Feng Teng, Wei-Cheng Wu, Yu-Jen Wang
  • Patent number: 11909522
    Abstract: Disclosed are systems, methods, and non-transitory computer-readable storage media for monitoring application health via correctable errors. The method includes identifying, by a network device, a network packet associated with an application and detecting an error associated with the network packet. In response to detecting the error, the network device increments a counter associated with the application, determines an application score based at least in part on the counter, and telemeters the application score to a controller. The controller can generate a graphical interface based at least in part on the application score and a timestamp associated with the application score, wherein the graphical interface depicts a trend in correctable errors experienced by the application over a network.
    Type: Grant
    Filed: December 21, 2022
    Date of Patent: February 20, 2024
    Assignee: Cisco Technology, Inc.
    Inventors: Keerthi Manjunathan Swarnamanjunathan, Chih-Tsung Huang, Kelvin Chan, Wei-Jen Huang
  • Patent number: 11882024
    Abstract: The present technology is directed to a system and method for application aware management and recovery of link failures resulting from excessive errors observed on the link. One aspect of the proposed technology is based on identification of link errors associated with application-specific data patterns traversing link. Other aspects involve corrective actions based on relocation or modification of specific application traffic to thereby alleviate the observed excessive link errors and prevent a link failure or shut down. Relocation may involve moving the source application to a different virtual machine/container/physical device or rerouting application traffic by updating relevant routing protocols. Modification may involve harmlessly changing payload data pattern to remove data-pattern dependent signal attenuation.
    Type: Grant
    Filed: June 18, 2018
    Date of Patent: January 23, 2024
    Assignee: Cisco Technology, Inc.
    Inventors: Chih-Tsung Huang, Wei-Jen Huang
  • Publication number: 20230123918
    Abstract: Disclosed are systems, methods, and non-transitory computer-readable storage media for monitoring application health via correctable errors. The method includes identifying, by a network device, a network packet associated with an application and detecting an error associated with the network packet. In response to detecting the error, the network device increments a counter associated with the application, determines an application score based at least in part on the counter, and telemeters the application score to a controller. The controller can generate a graphical interface based at least in part on the application score and a timestamp associated with the application score, wherein the graphical interface depicts a trend in correctable errors experienced by the application over a network.
    Type: Application
    Filed: December 21, 2022
    Publication date: April 20, 2023
    Inventors: Keerthi Manjunathan Swarnamanjunathan, Chih-Tsung Huang, Kelvin Chan, Wei-Jen Huang
  • Patent number: 11463383
    Abstract: Presented herein are techniques for redacting mirrored network packets prior to providing the mirrored packets to an intended recipient application, such as a third-party analysis application. More specifically, a multi-destination packet redaction device obtains mirrored network traffic that comprises one or more mirrored network packets. The multi-destination packet redaction device filters the mirrored network traffic to determine an intended recipient application of the one or more mirrored network packets and applies a redaction process to redact one or more portions of at least one of the one or more mirrored network packets. The redaction process is customized based on one or more attributes of the intended recipient application.
    Type: Grant
    Filed: February 1, 2021
    Date of Patent: October 4, 2022
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: Chih-Tsung Huang, Wei-Jen Huang, Kelvin Chan, Chiapeng Wu
  • Patent number: 11258273
    Abstract: A charger circuit which supplies a charging power to charge a battery circuit, includes: a conversion switch circuit, at least one capacitor and a conversion control circuit. The conversion switch circuit is coupled between a charging power and a ground level and includes conversion switches connected in series. The conversion switch circuit has battery voltage balancing nodes electrically connected to the battery circuit, such that each battery is electrically connected between two of the battery voltage balancing nodes. The conversion control circuit is coupled to the conversion switch circuit and provides operation signals to the conversion switch circuit, to respectively control the corresponding conversion switches, so that the capacitor is periodically connected in parallel to each battery of the battery circuit, thereby balancing the battery voltages of the batteries.
    Type: Grant
    Filed: February 11, 2020
    Date of Patent: February 22, 2022
    Assignee: RICHTEK TECHNOLOGY CORPORATION
    Inventors: Wei-Jen Huang, Shun-Yu Huang, Tsung-Wei Huang, Shui-Mu Lin
  • Publication number: 20210344444
    Abstract: Disclosed are systems, methods, and non-transitory computer-readable storage media for monitoring application health via correctable errors. The method includes identifying, by a network device, a network packet associated with an application and detecting an error associated with the network packet. In response to detecting the error, the network device increments a counter associated with the application, determines an application score based at least in part on the counter, and telemeters the application score to a controller. The controller can generate a graphical interface based at least in part on the application score and a timestamp associated with the application score, wherein the graphical interface depicts a trend in correctable errors experienced by the application over a network.
    Type: Application
    Filed: July 19, 2021
    Publication date: November 4, 2021
    Inventors: Keerthi Manjunathan Swarnamanjunathan, Chih-Tsung Huang, Kelvin Chan, Wei-Jen Huang
  • Patent number: 11070311
    Abstract: Disclosed are systems, methods, and non-transitory computer-readable storage media for monitoring application health via correctable errors. The method includes identifying, by a network device, a network packet associated with an application and detecting an error associated with the network packet. In response to detecting the error, the network device increments a counter associated with the application, determines an application score based at least in part on the counter, and telemeters the application score to a controller. The controller can generate a graphical interface based at least in part on the application score and a timestamp associated with the application score, wherein the graphical interface depicts a trend in correctable errors experienced by the application over a network.
    Type: Grant
    Filed: January 24, 2020
    Date of Patent: July 20, 2021
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: Keerthi Manjunathan Swarnamanjunathan, Chih-Tsung Huang, Kelvin Chan, Wei-Jen Huang
  • Publication number: 20210160196
    Abstract: Presented herein are techniques for redacting mirrored network packets prior to providing the mirrored packets to an intended recipient application, such as a third-party analysis application. More specifically, a multi-destination packet redaction device obtains mirrored network traffic that comprises one or more mirrored network packets. The multi-destination packet redaction device filters the mirrored network traffic to determine an intended recipient application of the one or more mirrored network packets and applies a redaction process to redact one or more portions of at least one of the one or more mirrored network packets. The redaction process is customized based on one or more attributes of the intended recipient application.
    Type: Application
    Filed: February 1, 2021
    Publication date: May 27, 2021
    Inventors: Chih-Tsung Huang, Wei-Jen Huang, Kelvin Chan, Chiapeng Wu
  • Patent number: RE48645
    Abstract: Techniques are presented herein to facilitate the monitoring of occupancy of a buffer in a network device. Packets are received at a network device. Information is captured describing occupancy of the buffer caused by packet flow through the buffer in the network device. Analytics packets are generated containing the information. The analytics packets from the network device for retrieval of the information contained therein for analysis, replay of buffer occupancy, etc.
    Type: Grant
    Filed: May 1, 2019
    Date of Patent: July 13, 2021
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: Thomas J. Edsall, Yue J. Yang, Wei-Jen Huang, Chih-Tsung Huang
  • Patent number: RE49806
    Abstract: Techniques are presented herein to facilitate latency measurements in a networking environment. A first network device receives a packet for transport within a network domain that comprises a plurality of network devices. The plurality of network devices have a common time reference, that is, they are time synchronized. The first network device generates timestamp information indicating time of arrival of the packet at the first network device. The first network device inserts into the packet a tag that comprises at least a first subfield and a second subfield. The first subfield comprising a type indicator to signify to other network devices in the network domain that the tag includes timestamp information, and the second subfield includes the timestamp information. The first network device sends the packet from to into the network domain to another network device. Other network devices which receive that packet can make latency measurements.
    Type: Grant
    Filed: May 1, 2019
    Date of Patent: January 16, 2024
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: Thomas J. Edsall, Wei-Jen Huang, Chih-Tsung Huang, Yichou Lin