Abstract: An optical element driving mechanism is provided and includes a fixed assembly, a movable assembly, a driving assembly and a stopping assembly. The fixed assembly has a main axis. The movable assembly is configured to connect an optical element, and the movable assembly is movable relative to the fixed assembly. The driving assembly is configured to drive the movable assembly to move relative to the fixed assembly. The stopping assembly is configured to limit the movement of the movable assembly relative to the fixed assembly within a range of motion.

Abstract: A layout includes a first and a second standard cells abutting along a boundary line. The first cell includes first fins. An edge of the first fins closest to and away from the boundary line by a distance D1. A first gate line over-crossing the first fins protrudes from the edge by a length L1. The second cell includes second fins. An edge of the second fins closest to and away from the boundary line by a distance D2. A second gate line over-crossing the second fins protrudes from the edge by a length L2. Two first dummy gate lines at two sides of the first fins and two second dummy lines at two sides of the second fins are respectively away from the boundary line by a distance S. The lengths L1 and L2, the distances S, D1 and D2 have the relationships: L1?D1?S, L2?D2?S, and D1?D2.

Abstract: Semiconductor dies of a semiconductor die package are directly bonded, and a top metal region may be formed over the semiconductor dies. A plurality of conductive terminals may be formed over the top metal region. The conductive terminals are formed of copper (Cu) or another material that enables low-temperature deposition process techniques, such as electroplating, to be used to form the conductive terminal. In this way, the conductive terminals of the semiconductor die packages described herein may be formed at a relatively low temperature. This reduces the likelihood of thermal deformation of semiconductor dies in the semiconductor die packages. The reduced thermal deformation reduces the likelihood of warpage, breakage, and/or other types of damage to the semiconductor dies of the semiconductor die packages, which may increase performance and/or increase yield of semiconductor die packages.

Abstract: A semiconductor die package includes an inductor-capacitor (LC) semiconductor die that is directly bonded with a logic semiconductor die. The LC semiconductor die includes inductors and capacitors that are integrated into a single die. The inductors and capacitors of the LC semiconductor die may be electrically connected with transistors and other logic components on the logic semiconductor die to form a voltage regulator circuit of the semiconductor die package. The integration of passive components (e.g., the inductors and capacitors) of the voltage regulator circuit into a single semiconductor die reduces signal propagation distances in the voltage regulator circuit, which may increase the operating efficiency of the voltage regulator circuit, may reduce the formfactor for the semiconductor die package, may reduce parasitic capacitance and/or may reduce parasitic inductance in the voltage regulator circuit (thereby improving the performance of the voltage regulator circuit), among other examples.

Abstract: A semiconductor device according to embodiments of the present disclosure includes a first die including a first bonding layer and a second die including a second hybrid bonding layer. The first bonding layer includes a first dielectric layer and a first metal coil embedded in the first dielectric layer. The second bonding layer includes a second dielectric layer and a second metal coil embedded in the second dielectric layer. The second hybrid bonding layer is bonded to the first hybrid bonding layer such that the first dielectric layer is bonded to the second dielectric layer and the first metal coil is bonded to the second metal coil.

Abstract: A semiconductor device includes a first die having a first bonding layer; a second die having a second bonding layer disposed over and bonded to the first bonding layer; a plurality of bonding members, wherein each of the plurality of bonding members extends within the first bonding layer and the second bonding layer, wherein the plurality of bonding members includes a connecting member electrically connected to a first conductive pattern in the first die and a second conductive pattern in the second die, and a dummy member electrically isolated from the first conductive pattern and the second conductive pattern; and an inductor disposed within the first bonding layer and the second bonding layer. A method of manufacturing a semiconductor device includes bonding a first inductive coil of a first die to a second inductive coil of a second die to form an inductor.

Abstract: A semiconductor package includes a first semiconductor device and a second semiconductor device. The first semiconductor device includes a first alignment pattern having a plurality of first scale patterns arranged in a first direction. The second semiconductor device is mounted over the first semiconductor device and includes a second alignment pattern having a plurality of second scale patterns arranged in a second direction parallel to the first direction, and a scale pitch of the first scale patterns is different from a scale pitch of the second scale patterns.

Abstract: An ultrasonic transducer includes a piezoceramic element with a first surface and a second surface opposite to each other through the piezoceramic element and a lateral surface connecting the first surface and the second surface, an acoustic matching layer with a third surface and a fourth surface opposite to each other through the acoustic matching layer and the third surface connecting with the second surface of the piezoceramic element, a first damping element with a fifth surface and a sixth surface opposite to each other through the first damping element and the sixth surface connecting with the first surface of the piezoceramic element, and a second damping element encapsulating the first damping element and the lateral surface of the piezoceramic element.

Abstract: A semiconductor package includes a first semiconductor device and a second semiconductor device. The first semiconductor device includes a first alignment pattern having a plurality of first scale patterns arranged in a first direction. The second semiconductor device is mounted over the first semiconductor device and includes a second alignment pattern having a plurality of second scale patterns arranged in a second direction parallel to the first direction, and a scale pitch of the first scale patterns is different from a scale pitch of the second scale patterns.

Abstract: A detection device for a spindle of a machine tool is provided, wherein the spindle includes an insertion hole. The detection device includes a contact housing, a main housing, a sensor, and a process module. The contact housing has a first chamber, and the first chamber has an inner surface. The main housing is connected to the contact housing, and has a second chamber communicated with the first chamber. The sensor is disposed in the first chamber and connected to the inner surface. The process module is disposed in the second chamber and electrically connected to the sensor. When the contact housing is inserted into the insertion hole of the spindle, the sensor is configured to detect the deformation of the contact housing and generate a detection signal. The process module generates a determination signal according to the detection signal.

Abstract: A platform structure for manufacturing a scaffold for use in tissue engineering, comprising a frame; a ring-shaped thermally conductive member fixedly disposed in the frame; a thermally conductive platform centrally movably disposed in the ring-shaped thermally conductive member and having edges in direct contact with inner walls of the ring-shaped thermally conductive member, wherein the thermally conductive platform and the ring-shaped thermally conductive member together define a space of a variable depth; a vertically movable mechanism connected to a bottom of the thermally conductive platform and adapted to drive the thermally conductive platform to sink and thus increase gradually the depth of the space; and a low temperature generating mechanism connected to the ring-shaped thermally conductive member and the thermally conductive platform to cool down the ring-shaped thermally conductive member and the thermally conductive platform, to prevent deformation and ensure uniform dimensions of tall scaffolds

Abstract: A manufacturing apparatus for use in the low-temperature high-speed manufacturing of a support structure is introduced. The support structure thus manufactured is for supporting a low-temperature manufacturing scaffold for use in tissue engineering.

Abstract: A platform structure for manufacturing a scaffold for use in tissue engineering, comprising a frame; a ring-shaped thermally conductive member fixedly disposed in the frame; a thermally conductive platform centrally movably disposed in the ring-shaped thermally conductive member and having edges in direct contact with inner walls of the ring-shaped thermally conductive member, wherein the thermally conductive platform and the ring-shaped thermally conductive member together define a space of a variable depth; a vertically movable mechanism connected to a bottom of the thermally conductive platform and adapted to drive the thermally conductive platform to sink and thus increase gradually the depth of the space; and a low temperature generating mechanism connected to the ring-shaped thermally conductive member and the thermally conductive platform to cool down the ring-shaped thermally conductive member and the thermally conductive platform, to prevent deformation and ensure uniform dimensions of tall scaffolds

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a first material layer on the substrate; forming a stop layer on the first material layer; forming a second material layer on the stop layer; and performing a planarizing process to remove the second material layer, the stop layer, and part of the first material layer for forming a gate layer.

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a fin-shaped structure thereon; forming an epitaxial layer on the fin-shaped structure; forming a first contact etch stop layer (CESL) on the epitaxial layer; forming a source/drain region in the epitaxial layer; and forming a second CESL on the first CESL.

Abstract: A method for performance optimization of protein chips produced under an external electric field applied in different directions and a device that provides the external electric field in different directions are revealed. Firstly a plurality of protein chips is produced under an external electric field applied in different directions. Then a binding force between protein molecule on the protein chip and a ligand is measured and compared. Thus an angle of the external electric field applied that achieves performance optimization while using the protein molecule to produce the protein chips is found out. The device providing the external electric field in different directions includes a rotatable electric field support rotating around a carrier used for loading the protein chips. The electric field support is disposed with electrodes for providing the protein chips on the carrier the external electric field in different directions.

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a fin-shaped structure thereon; forming an epitaxial layer on the fin-shaped structure; forming a first contact etch stop layer (CESL) on the epitaxial layer; forming a source/drain region in the epitaxial layer; and forming a second CESL on the first CESL.

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a first material layer on the substrate; forming a stop layer on the first material layer; forming a second material layer on the stop layer; and performing a planarizing process to remove the second material layer, the stop layer, and part of the first material layer for forming a gate layer.

Abstract: A semiconductor process wafer having substantially co-planar active areas and a laser marked area in an adjacent inactive area and method for forming the same to eliminate a step height and improve a subsequent patterning process over the active areas wherein an inactive area trench is formed overlying the laser marked area in parallel with formation of STI trenches in the active area whereby the active areas and the inactive area are formed substantially co-planar without a step height.

Abstract: A semiconductor process wafer having substantially co-planar active areas and a laser marked area in an adjacent inactive area and method for forming the same to eliminate a step height and improve a subsequent patterning process over the active areas wherein an inactive area trench is formed overlying the laser marked area in parallel with formation of STI trenches in the active area whereby the active areas and the inactive area are formed substantially co-planar without a step height.