Abstract: The present invention discloses an analog to digital conversion (ADC) apparatus having quick conversion mechanism. Each of ADC circuits receives a previous higher-bit conversion result to perform prediction to generate a current higher-bit conversion result, performs conversion on an input analog signal according to a sampling clock that has a frequency at least twice of the frequency of the input analog signal based on a successive-approximation mechanism to generate a current lower-bit conversion result, and combines the current higher-bits and current lower-bit conversion results to generate a current conversion result and output a remained signal amount as a residue. A noise-shaping circuit performs calculation based on the residue to generate a noise-shaping reference signal. Each of the ADC circuits combines the current conversion result and the noise-shaping reference signal to generate an output digital signal.

Abstract: The present invention discloses a SAADC circuit having optimized linearity. A lower-bit capacitor array includes lower-bit capacitors. A higher-bit capacitor array includes unit capacitors. In an initializing mode, a control circuit sorts the unit capacitors according to unit capacitances thereof such that the unit capacitors are configured to be higher-bit capacitors having a linearity parameter within a predetermined range. In an operation mode, the capacitor array receives an analog input signal and a reference voltage to generate an analog output signal, a comparator generates a comparison result according to the analog output signal and the control circuit generates an enabling signal according to the comparison result based on the successive approximation mechanism to selectively enable the higher-bit and the lower-bit capacitors to connect to the reference voltage by using the capacitor enabling circuit and outputs a digital output signal according to the final comparison result.

Abstract: A voltage regulation integrated circuit (IC) includes a first transistor, a feedback circuit, a bias circuit, an amplifier circuit, and a transient coupling circuit. The first transistor is configured to generate an output voltage according to an input voltage and a control voltage. The feedback circuit is configured to generate a feedback voltage according to the output voltage. The output voltage includes an AC component. The bias circuit is configured to generate a first bias voltage. The amplifier circuit is configured to generate the control voltage according to the first bias voltage and the feedback voltage. The transient coupling circuit is configured to generate a coupling voltage according to the AC component and to assist the change of the first bias voltage according to the coupling voltage, so that the output voltage is maintained at a voltage level.

Abstract: An analog-to-digital converter includes a switch circuit, a first capacitor array, a second capacitor array and a comparator. A method of operating the analog-to-digital converter includes switching a swap signal to a first level in a first sampling period for the switch circuit to couple the first capacitor array to a first input terminal of the comparator and a first signal source, and couple the second capacitor array to a second input terminal of the comparator and a second signal source, and switching the swap signal to a second level in a second sampling period for the switch circuit to couple the first capacitor array to the second input terminal of the comparator and the second signal source, and couple the second capacitor array to the first input terminal of the comparator and the first signal source.

Abstract: A method of operating an analog-to-digital converter includes in a first conversion period, a comparator generating a first comparison result, a first selection circuit switching a voltage output to a first capacitor of a set of larger capacitor of a first capacitor array, and a second selection circuit switching a voltage output to a second capacitor of a set of larger capacitor of a second capacitor array, and in a second conversion period after the first conversion period, the comparator generating a second comparison result different from the first comparison result, the first selection circuit switching back the voltage output to a first capacitor portion of the first capacitor of the set of larger capacitor of the first capacitor array, and the second selection circuit switching back the voltage output to a first capacitor portion of the second capacitor of the set of larger capacitor of the second capacitor array.

Abstract: An analog-to-digital converter includes a switch circuit, a first capacitor array, a second capacitor array and a comparator. A method of operating the analog-to-digital converter includes switching a swap signal to a first level in a first sampling period for the switch circuit to couple the first capacitor array to a first input terminal of the comparator and a first signal source, and couple the second capacitor array to a second input terminal of the comparator and a second signal source, and switching the swap signal to a second level in a second sampling period for the switch circuit to couple the first capacitor array to the second input terminal of the comparator and the second signal source, and couple the second capacitor array to the first input terminal of the comparator and the first signal source.

Abstract: A method of operating an analog-to-digital converter includes in a first conversion period, a comparator generating a first comparison result, a first selection circuit switching a voltage output to a first capacitor of a set of larger capacitor of a first capacitor array, and a second selection circuit switching a voltage output to a second capacitor of a set of larger capacitor of a second capacitor array, and in a second conversion period after the first conversion period, the comparator generating a second comparison result different from the first comparison result, the first selection circuit switching back the voltage output to a first capacitor portion of the first capacitor of the set of larger capacitor of the first capacitor array, and the second selection circuit switching back the voltage output to a first capacitor portion of the second capacitor of the set of larger capacitor of the second capacitor array.

Abstract: A method of operating an analog-to-digital converter includes in a first sampling stage, switching a swap signal to a first level for a first selection circuit to reset a first capacitor array according to a first voltage configuration and for a second selection circuit to reset a second capacitor array according to the first voltage configuration, and in a second sampling stage, switching the swap signal to a second level for the first selection circuit to reset the first capacitor array according to the second voltage configuration and for the second selection circuit to reset the second capacitor array according to the second voltage configuration. A control logic circuit is used to switch the swap signal between the first level and the second level in a uniform order in a plurality of sampling stages.

Abstract: A digital-to-analog converter circuit generates an analog transmitted signal according to a digital transmitted signal. A first echo canceller circuit generates a first echo cancelling signal according to the digital transmitted signal. A processor circuit generates an analog processed signal according to the analog transmitted signal, the first echo cancelling signal, and a received signal. An analog-to-digital converter circuit generates a digital value according to the analog processed signal and two slicer levels of a plurality of slicer levels. A storage circuit stores a look-up table. The look-up table records an offset value corresponding to the digital value. The storage circuit further outputs a first output signal according to the digital value and the offset value. The offset value is updated according to an error value associated with the first output signal.

Abstract: The present invention discloses an analog to digital conversion (ADC) apparatus having quick conversion mechanism. Each of ADC circuits receives a previous higher-bit conversion result to perform prediction to generate a current higher-bit conversion result, performs conversion on an input analog signal according to a sampling clock that has a frequency at least twice of the frequency of the input analog signal based on a successive-approximation mechanism to generate a current lower-bit conversion result, and combines the current higher-bits and current lower-bit conversion results to generate a current conversion result and output a remained signal amount as a residue. A noise-shaping circuit performs calculation based on the residue to generate a noise-shaping reference signal. Each of the ADC circuits combines the current conversion result and the noise-shaping reference signal to generate an output digital signal.

Abstract: A control circuit of a pipeline analog-to-digital converter (ADC) is provided. The pipeline ADC includes a multiplying digital-to-analog converter (MDAC) which includes a capacitor. The control circuit includes six switches and two buffer circuits. The first and second switches are respectively coupled between one end of the capacitor and the first and second reference voltages. The output terminals of the first and second buffer circuits are respectively coupled to the first and second switches. The input terminal of the first buffer circuit is coupled to the third reference voltage through the third switch, or receives a control signal through the fifth switch. The input terminal of the second buffer circuit is coupled to the fourth reference voltage through the fourth switch, or receives the control signal through the sixth switch. The first and second reference voltages are different, and the first and second switches are not turned on simultaneously.

Abstract: A method of operating an analog-to-digital converter includes in a first sampling stage, switching a swap signal to a first level for a first selection circuit to reset a first capacitor array according to a first voltage configuration and for a second selection circuit to reset a second capacitor array according to the first voltage configuration, and in a second sampling stage, switching the swap signal to a second level for the first selection circuit to reset the first capacitor array according to the second voltage configuration and for the second selection circuit to reset the second capacitor array according to the second voltage configuration. A control logic circuit is used to switch the swap signal between the first level and the second level in a uniform order in a plurality of sampling stages.

Abstract: A control circuit of a pipeline analog-to-digital converter (ADC) is provided. The pipeline ADC includes a multiplying digital-to-analog converter (MDAC) which includes a capacitor. The control circuit includes six switches and two buffer circuits. The first and second switches are respectively coupled between one end of the capacitor and the first and second reference voltages. The output terminals of the first and second buffer circuits are respectively coupled to the first and second switches. The input terminal of the first buffer circuit is coupled to the third reference voltage through the third switch, or receives a control signal through the fifth switch. The input terminal of the second buffer circuit is coupled to the fourth reference voltage through the fourth switch, or receives the control signal through the sixth switch. The first and second reference voltages are different, and the first and second switches are not turned on simultaneously.

Abstract: A low voltage inverter-based amplifier includes a first inverter-based amplification module, a second inverter-based amplification module, an inverter-based feedforward module, and an inverter-based common mode detector. The first inverter-based amplification module receives an input signal. The second inverter-based amplification module receives the input signal through the inverter-based feedforward module, and receives a first output signal from the first inverter-based amplification module. The inverter-based common mode detector receives an amplified signal from the second inverter-based amplification module, and outputs a feedback signal to the second inverter-based amplification module. Since the first and the second inverter-based amplification modules are both inverter-based, the supply voltage of the low voltage inverter-based amplifier is provided to supply one PMOS and one NMOS for normal operation.

Abstract: A frequency-modulated continuous-wave radar system includes a waveform generator, a delta-sigma modulation circuit, a voltage controlled oscillator, a frequency divider circuit, a control circuit, an injection locked oscillator, a power amplifier circuit, a first power detection circuit, a second power detection circuit, a third power detection circuit, and a calibration engine circuit. The waveform generator, the delta-sigma modulation circuit, the voltage controlled oscillator, the frequency divider circuit, and the control circuit form a phase locked loop.

Abstract: An oscillating circuit has an injection-locked oscillator (ILO) and a calibration circuit. The ILO has a Gm cell and an LC tank. A first node of the Gm cell receives a first injection signal, and a second node of the Gm cell receives a second injection signal. The first injection signal and the second injection signal are differential signals. The Gm cell provides a negative resistance between a first output end and a second output end of the Gm cell. When the calibration circuit tunes a resonant frequency of the LC tank of the ILO, the magnitude of the negative resistance is reduced to control the ILO to stop self-oscillating. After finishing tuning the resonant frequency of the LC tank, the calibration circuit controls the ILO to start self-oscillating by increasing the magnitude of the negative resistance.

Abstract: A method for enhancing linearity of the receiver front-end system includes receiving a radio frequency signal by an antenna, converting the radio frequency signal to first differential signals by a transformer module, adjusting frequencies of the first differential signals to generate second differential signals by a mixer module, detecting a common signal in order to reduce a common error of the second differential signals, and generating third differential signals according to a reference signal after the common error is reduced from the second differential signals. The first differential signals, the second differential signals, and the third differential signals are unbalanced.

Abstract: A method for enhancing linearity of the receiver front-end system includes receiving a radio frequency signal by an antenna, converting the radio frequency signal to first differential signals by a transformer module, adjusting frequencies of the first differential signals to generate second differential signals by a mixer module, detecting a common signal in order to reduce a common error of the second differential signals, and generating third differential signals according to a reference signal after the common error is reduced from the second differential signals. The first differential signals, the second differential signals, and the third differential signals are unbalanced.

Abstract: A divider-less phase locked loop (PLL) includes a phase frequency detector (PFD), a charge pump (CP), a voltage controlled oscillator (VCO), a delay unit, and a clock gating unit. The PFD is electrically connected to the VCO through the CP, and the CP outputs a voltage control signal to the VCO. The VCO generates an output signal. The delay unit receives and delays a reference signal to generate a delay signal. The clock gating unit samples the output signal according to the delay signal. Since the clock gating unit samples the output signal according to the delay signal, the divider-less PLL does not need to include a divider to divide a frequency of the output signal. Therefore, power consumption of the divider-less PLL can be reduced.

Abstract: An oscillating circuit has an injection-locked oscillator (ILO) and a calibration circuit. The ILO has a Gm cell and an LC tank. A first node of the Gm cell receives a first injection signal, and a second node of the Gm cell receives a second injection signal. The first injection signal and the second injection signal are differential signals. The Gm cell provides a negative resistance between a first output end and a second output end of the Gm cell. When the calibration circuit tunes a resonant frequency of the LC tank of the ILO, the magnitude of the negative resistance is reduced to control the ILO to stop self-oscillating. After finishing tuning the resonant frequency of the LC tank, the calibration circuit controls the ILO to start self-oscillating by increasing the magnitude of the negative resistance.