Patents by Inventor Wei-Kang Liu
Wei-Kang Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11977256Abstract: Various embodiments of the present disclosure are directed towards a semiconductor package comprising optically coupled integrated circuit (IC) chips. A first IC chip and a second IC chip overlie a substrate at a center of the substrate. A photonic chip overlies the first and second IC chips and is electrically coupled to the second IC chip. A laser device chip overlies the substrate, adjacent to the photonic chip and the second IC chip, at a periphery of the substrate. The photonic chip is configured to modulate a laser beam from the laser device chip in accordance with an electrical signal from the second IC chip and to provide the modulated laser beam to the first IC chip. This facilitates optical communication between the first IC chip to the second IC chip. Various embodiments of the present disclosure are further directed towards simultaneously aligning and bonding constituents of the semiconductor package.Type: GrantFiled: May 23, 2022Date of Patent: May 7, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Tsung Shih, Hau-Yan Lu, Wei-Kang Liu, Yingkit Felix Tsui
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Patent number: 11948702Abstract: A radiation source apparatus includes a vessel, a laser source, a collector, a horizontal obscuration bar, and a reflective mirror. The vessel has an exit aperture. The laser source is configured to emit a laser beam to excite a target material to form a plasma. The collector is disposed in the vessel and configured to collect a radiation emitted by the plasma and to reflect the collected radiation to the exit aperture of the vessel. The horizontal obscuration bar extends from a sidewall of the vessel at least to a position between the laser source and the exit aperture of the vessel. The reflective mirror is in the vessel and connected to the horizontal obscuration bar.Type: GrantFiled: May 5, 2023Date of Patent: April 2, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wei-Chung Tu, Sheng-Kang Yu, Shang-Chieh Chien, Li-Jui Chen, Heng-Hsin Liu
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Publication number: 20240045141Abstract: A semiconductor structure includes a substrate, a grating coupler structure over the substrate, a multi-layers film structure over the grating coupler structure. The multi-layers film structure include a first layer including a first refractive index, a second layer over the first layer and including a second refractive index and a third layer over the second layer and including a third refractive index. The second refractive index is greater than the first refractive index and is greater than the third refractive index of the third layer, and a thickness of each layer of the multi-layers film structure is within a range from ?/4 to ?2, ? is a wavelength of light.Type: ApplicationFiled: August 3, 2022Publication date: February 8, 2024Inventors: CHIH-TSUNG SHIH, WEI-KANG LIU, SUI-YING HSU, JING-HWANG YANG, YINGKIT FELIX TSUI
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Publication number: 20240045240Abstract: A method includes receiving a silicon substrate; forming a first doped region and a second doped region in the silicon substrate; forming a third doped region and fourth doped region on upper portions of the first doped region and the second doped region, respectively; and patterning the silicon substrate to form an optical modulator. The optical modulator includes: a first section; a second section and a third section at least formed from the first and second doped regions, respectively; a fourth section, including a first height less than that of the first section and the second section and arranged between the first section and the second section, the fourth section being an undoped region; and a fifth section immediately adjacent to the fourth section, the fifth section including a height less than that of the first section and the second section and different from the first height.Type: ApplicationFiled: August 2, 2022Publication date: February 8, 2024Inventors: CHIH-TSUNG SHIH, FENG YUAN, WEI-KANG LIU, YINGKIT FELIX TSUI
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Publication number: 20240045143Abstract: An optical waveguide structure of a semiconductor photonic device includes a first semiconductor waveguide, a second semiconductor waveguide, and an air seam between the first and second semiconductor waveguides. The semiconductor waveguides extend in a first direction, and a plurality of air seams extend in a second direction. Each of the air seams is disposed between two adjacent semiconductor waveguides. A distance between the two adjacent semiconductor waveguides is less than a width of each semiconductor waveguide.Type: ApplicationFiled: August 3, 2022Publication date: February 8, 2024Inventors: CHIH-TSUNG SHIH, HAU-YAN LU, WEI-KANG LIU, YINGKIT FELIX TSUI
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Publication number: 20240019639Abstract: An edge coupler, a waveguide structure and a method for forming a waveguide structure are provided. The edge coupler includes a substrate, a first cladding layer, a core layer and a first anti-reflection coating layer. The first cladding layer has a second sidewall aligned with a first sidewall of the substrate. The core layer has a third sidewall aligned with the second sidewall. The anti-reflection coating layer lines the first sidewall, the second sidewall and the third sidewall. A thickness of the anti-reflection coating layer varies along the first sidewall, the second sidewall and the third sidewall.Type: ApplicationFiled: July 13, 2022Publication date: January 18, 2024Inventors: WEI-KANG LIU, CHIH-TSUNG SHIH, HAU-YAN LU, YINGKIT FELIX TSUI
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Publication number: 20240012199Abstract: Some implementations described herein include a photonics integrated circuit device including a photonics structure. The photonics structure includes a waveguide structure and an optical attenuator structure. In some implementation, the optical attenuator structure is formed on an end region of the waveguide structure and includes a metal material or a doped material. In some implementations, the optical attenuator structure includes a gaussian doping profile within a portion of the waveguide structure. The optical attenuator structure may absorb electromagnetic waves at the end of the waveguide structure with an efficiency that is improved relative to a spiral optical attenuator structure or metal cap optical attenuator structure.Type: ApplicationFiled: July 8, 2022Publication date: January 11, 2024Inventors: Wei-kang LIU, Chih-Tsung SHIH, Hau-Yan LU, YingKit Felix TSUI, Lee-Shian JENG
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Publication number: 20240004131Abstract: A semiconductor structure includes a waveguide and an optical attenuator. The waveguide is disposed over an insulating layer and configured to guide light. The optical attenuator is connected to the waveguide. The optical attenuator has a first surface and a second surface opposite the first surface, and a cross-sectional width of the optical attenuator decreases from the first surface to the second surface.Type: ApplicationFiled: July 1, 2022Publication date: January 4, 2024Inventors: WEI-KANG LIU, LEE-SHIAN JENG, CHIH-TSUNG SHIH, HAU-YAN LU, YINGKIT FELIX TSUI
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Publication number: 20230387334Abstract: A method for manufacturing an integrated circuit device is provided. The method includes: providing a photonic structure including an insulating structure and an optical coupler embedded in the insulating structure; and removing a portion of the insulating structure to expose a coupling surface of the optical coupler and form a light reflective structure corresponding to the coupling surface.Type: ApplicationFiled: May 26, 2022Publication date: November 30, 2023Inventors: WEI-KANG LIU, CHIH-TSUNG SHIH, HAU-YAN LU, YINGKIT FELIX TSUI
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Patent number: 11817656Abstract: An electrical connector includes an insulating body and first through eighth terminals sequentially arranged in a lateral direction in the insulating body, wherein the first and second terminals, the third and sixth terminals, the fourth and fifth terminals, and the seventh and eighth terminals are respectively used to transmit a pair of differential signals, each terminal including: a mating portion for mating to a mating connector; a tail portion opposite to the mating portion; and a connecting portion connected therebetween, the connecting portions of the third terminal to the fifth terminal are all provided with a coupling portion; wherein the coupling portions of the third through fifth terminals are in three different planes, respectively, and the coupling portion of the fifth terminal and the coupling portion of the third terminal at least partially overlap in a longitudinal direction perpendicular to the lateral direction.Type: GrantFiled: January 13, 2022Date of Patent: November 14, 2023Assignees: FOXCONN (KUNSHAN) COMPUTER CONNECTOR CO., LTD., FOXCONN INTERCONNECT TECHNOLOGY LIMITEDInventors: Yong-Chun Xu, Hung-Chi Yu, Chih-Ching Hsu, Wei-Kang Liu, Chin-Jung Wu, Xiao-Qin Zheng
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Publication number: 20230314718Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit. The integrated circuit includes a substrate having an upper face and a lower face. The upper face includes a central region and an outer sidewall that laterally surrounds the central region and that extends from the upper face to the lower face. An optical edge coupler is disposed over the upper face of the substrate and extends in a first direction from the central region toward the outer sidewall. An outer sidewall of the optical edge coupler corresponds to the outer sidewall of the substrate and has a concave surface or a convex surface.Type: ApplicationFiled: July 1, 2022Publication date: October 5, 2023Inventors: Wei-Kang Liu, Chih-Tsung Shih, Hau-Yan Lu, Yingkit Felix Tsui
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Publication number: 20230296834Abstract: A photonic device and related method for forming a photonic device. In some embodiments, a method of fabricating a photonic device includes forming a layer stack over a substrate. In some cases, the layer stack includes a lower cladding layer, a core layer disposed over the lower cladding layer, and an upper cladding layer disposed over the core layer. In some examples, the method further includes patterning the layer stack to form a waveguide for the photonic device. In some cases, the waveguide includes the core layer, and the core layer includes a lateral surface having a convex profile.Type: ApplicationFiled: June 7, 2022Publication date: September 21, 2023Inventors: Yuan-Sheng HUANG, Wei-Kang LIU
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Publication number: 20230273367Abstract: Various embodiments of the present disclosure are directed towards a semiconductor package comprising optically coupled integrated circuit (IC) chips. A first IC chip and a second IC chip overlie a substrate at a center of the substrate. A photonic chip overlies the first and second IC chips and is electrically coupled to the second IC chip. A laser device chip overlies the substrate, adjacent to the photonic chip and the second IC chip, at a periphery of the substrate. The photonic chip is configured to modulate a laser beam from the laser device chip in accordance with an electrical signal from the second IC chip and to provide the modulated laser beam to the first IC chip. This facilitates optical communication between the first IC chip to the second IC chip. Various embodiments of the present disclosure are further directed towards simultaneously aligning and bonding constituents of the semiconductor package.Type: ApplicationFiled: May 23, 2022Publication date: August 31, 2023Inventors: Chih-Tsung Shih, Hau-Yan Lu, Wei-Kang Liu, Yingkit Felix Tsui
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Publication number: 20220231461Abstract: An electrical connector includes an insulating body and first through eighth terminals sequentially arranged in a lateral direction in the insulating body, wherein the first and second terminals, the third and sixth terminals, the fourth and fifth terminals, and the seventh and eighth terminals are respectively used to transmit a pair of differential signals, each terminal including: a mating portion for mating to a mating connector; a tail portion opposite to the mating portion; and a connecting portion connected therebetween, the connecting portions of the third terminal to the fifth terminal are all provided with a coupling portion; wherein the coupling portions of the third through fifth terminals are in three different planes, respectively, and the coupling portion of the fifth terminal and the coupling portion of the third terminal at least partially overlap in a longitudinal direction perpendicular to the lateral direction.Type: ApplicationFiled: January 13, 2022Publication date: July 21, 2022Inventors: YONG-CHUN XU, HUNG-CHI YU, CHIH-CHING HSU, WEI-KANG LIU, CHIN-JUNG WU, XIAO-QIN ZHENG
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Patent number: 11387124Abstract: Provided is a wafer container including a frame having a first sidewall and a second sidewall extending along a YZ plane; a plurality of first support structures disposed on the first sidewall and arranged along a Z direction; and a plurality of second support structures disposed on the second sidewall and arranged along the Z direction. One of the plurality of first support structures is horizontally aligned with a corresponding second support structure to constitute a wafer holder. The wafer holder includes a plurality of island structures to hold a wafer in a XY plane, and the plurality of island structures are separated to each other along a X direction. A method for holding at least one wafer is also provided.Type: GrantFiled: September 28, 2020Date of Patent: July 12, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Kang Liu, Chi-Chung Jen, Jui-Ming Huang, Wan-Ting Liao
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Publication number: 20210013057Abstract: Provided is a wafer container including a frame having a first sidewall and a second sidewall extending along a YZ plane; a plurality of first support structures disposed on the first sidewall and arranged along a Z direction; and a plurality of second support structures disposed on the second sidewall and arranged along the Z direction. One of the plurality of first support structures is horizontally aligned with a corresponding second support structure to constitute a wafer holder. The wafer holder includes a plurality of island structures to hold a wafer in a XY plane, and the plurality of island structures are separated to each other along a X direction. A method for holding at least one wafer is also provided.Type: ApplicationFiled: September 28, 2020Publication date: January 14, 2021Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Kang Liu, Chi-Chung Jen, Jui-Ming Huang, Wan-Ting Liao
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Patent number: 10811291Abstract: Provided is a wafer container including a frame and at least a pair of the stents. The frame has opposite sidewalls. The at least a pair of the stents is respectively disposed on the sidewalls of the frame, wherein the at least a pair of the stents is configured to provide at least three supporting points to support at least one wafer. A method for holding at least one wafer is also provided.Type: GrantFiled: January 30, 2018Date of Patent: October 20, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Kang Liu, Chi-Chung Jen, Jui-Ming Huang, Wan-Ting Liao
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Publication number: 20190139792Abstract: Provided is a wafer container including a frame and at least a pair of the stents. The frame has opposite sidewalls. The at least a pair of the stents is respectively disposed on the sidewalls of the frame, wherein the at least a pair of the stents is configured to provide at least three supporting points to support at least one wafer. A method for holding at least one wafer is also provided.Type: ApplicationFiled: January 30, 2018Publication date: May 9, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wei-Kang Liu, Chi-Chung Jen, Jui-Ming Huang, Wan-Ting Liao
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Patent number: 10096931Abstract: The plug connector includes an insulative housing and a terminal module wherein the terminal module is able to be moveable relative to the housing via sliding or rotation or translation or even detachment so as to have the front mating portion of the terminal module independently mated with the thin receptacle connector or cooperate with the housing to be mated with the regular RJ-45 modular jack.Type: GrantFiled: April 29, 2016Date of Patent: October 9, 2018Assignee: FOXCONN INTERCONNECT TECHNOLOGY LIMITEDInventors: Terrance F. Little, Stephen Sedio, Wei-Hao Su, Sheng-Pin Gao, Chih-Ching Hsu, Wei-Kang Liu
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Patent number: D784930Type: GrantFiled: September 30, 2015Date of Patent: April 25, 2017Assignee: FOXCONN INTERCONNECT TECHNOLOGY LIMITEDInventors: Chih-Ching Hsu, Jun-Hua Hu, Wei-Kang Liu, Chao-Tung Huang, De-Ke Liu, Jin-Jun Ze