Patents by Inventor Wei Lai

Wei Lai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240178214
    Abstract: An integrated circuit includes a horizontal routing track in a first metal layer, and a backside routing track in a backside metal layer. The backside metal layer and the first metal layer are formed at opposite sides of a semiconductor substrate. The horizontal routing track is conductively connected to a first terminal of a first transistor without passing through a routing track in another metal layer. The backside routing track is conductively connected to a second terminal of the first transistor without passing through a routing track in another metal layer. One of the first terminal and the second terminal is a gate terminal of the first transistor while another one the first terminal and the second terminal is either a source terminal or a drain terminal of the first transistor.
    Type: Application
    Filed: February 1, 2024
    Publication date: May 30, 2024
    Inventors: Wei-An LAI, Shih-Wei PENG, Wei-Cheng LIN, Jiann-Tyng TZENG
  • Publication number: 20240178139
    Abstract: Apparatus and methods for generating a physical layout for a high density routing circuit are disclosed. An exemplary semiconductor structure includes: a gate structure; a plurality of first metal lines formed in a first dielectric layer below the gate structure; at least one first via formed in a second dielectric layer between the gate structure and the first dielectric layer; a plurality of second metal lines formed in a third dielectric layer over the gate structure; and at least one second via formed in a fourth dielectric layer between the gate structure and the third dielectric layer. Each of the at least one first via is electrically connected to the gate structure and a corresponding one of the plurality of first metal lines. Each of the at least one second via is electrically connected to the gate structure and a corresponding one of the plurality of second metal lines.
    Type: Application
    Filed: February 8, 2024
    Publication date: May 30, 2024
    Inventors: Wei-An LAI, Shih-Wei PENG, Wei-Cheng LIN, Jiann-Tyng TZENG
  • Publication number: 20240176143
    Abstract: A head-mounted display, controlling method, and non-transitory computer readable storage medium thereof are provided. The head-mounted display determines a first posture among a plurality of postures based on a plurality of real-time images. The head-mounted display generates a first gesture among a plurality of gestures corresponding to a user according to a plurality of inertial measurement parameters corresponding to a first body part of the user. The head-mounted display generates a control signal corresponding to a first output event among a plurality of output events based on the first gesture and the first gesture.
    Type: Application
    Filed: November 28, 2022
    Publication date: May 30, 2024
    Inventors: Chao-Hsiang Lai, Cheng-Han Hsieh, Tzu-Wei Huang
  • Publication number: 20240173080
    Abstract: A navigation system of a surgical robot includes an endoscope and a navigation device. The endoscope is configured to capture an internal image of a tissue. The navigation device is configured for: analyzing the internal image to obtain a depth information of the tissue; determining whether there are several passages in the tissue according to the depth information; and selecting the passage that conforms to a path planning setting when the passages appear in the tissue.
    Type: Application
    Filed: December 28, 2022
    Publication date: May 30, 2024
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Po-Kai WANG, Tseng-Wei LAI
  • Publication number: 20240170381
    Abstract: In some implementations, one or more semiconductor processing tools may form a metal cap on a metal gate. The one or more semiconductor processing tools may form one or more dielectric layers on the metal cap. The one or more semiconductor processing tools may form a recess to the metal cap within the one or more dielectric layers. The one or more semiconductor processing tools may perform a bottom-up deposition of metal material on the metal cap to form a metal plug within the recess and directly on the metal cap.
    Type: Application
    Filed: February 1, 2024
    Publication date: May 23, 2024
    Inventors: Chun-Hsien HUANG, Peng-Fu HSU, Yu-Syuan CAI, Min-Hsiu HUNG, Chen-Yuan KAO, Ken-Yu CHANG, Chun-I TSAI, Chia-Han LAI, Chih-Wei CHANG, Ming-Hsing TSAI
  • Publication number: 20240168266
    Abstract: An optical path folding element includes an optical portion, a connection portion, matte structures and a light blocking layer. The optical portion has an optical surface and two reflective surfaces. A light beam enters into the optical path folding element via the optical surface and is reflected inside the optical path folding element through the optical surface. Each reflective surface is configured to reflect the light beam again inside the optical path folding element. The connection portion has connection surfaces connected to the optical surface and the reflective surfaces. The matte structures are at least disposed on and integrally formed with the connection portion. Each unitary structure of the matte structures is tapered off and recessed from the connection portion, such that the outer surface of the connection portion has an undulating shape. The light blocking layer is at least disposed on the connection portion for blocking light.
    Type: Application
    Filed: October 3, 2023
    Publication date: May 23, 2024
    Applicant: LARGAN PRECISION CO., LTD.
    Inventors: Chen Wei FAN, Syuan Ruei LAI, Jyun-Jia CHENG, Ming-Ta CHOU
  • Publication number: 20240170591
    Abstract: A method of fabricating a halide perovskite having a general formula of ABX3, wherein A, B, and X are inorganic elements and X is a halide, the method including a vapor-liquid-solid process triggered by a catalyst formed from a noble metal; A nanowire of the halide perovskite and a photoelectronic device thereof
    Type: Application
    Filed: November 21, 2022
    Publication date: May 23, 2024
    Inventors: Chung Yin Johnny Ho, You Meng, Zhengxun Lai, Wei Wang
  • Patent number: 11989005
    Abstract: A system performs adaptive thermal ceiling control at runtime. The system includes computing circuits and a thermal management module. When detecting a runtime condition change that affects power consumption in the system, the thermal management module determines an adjustment to the thermal ceiling of a computing circuit, and increases the thermal ceiling of the computing circuit according to the adjustment.
    Type: Grant
    Filed: September 30, 2021
    Date of Patent: May 21, 2024
    Assignee: MediaTek Inc.
    Inventors: Bo-Jr Huang, Jia-Wei Fang, Jia-Ming Chen, Ya-Ting Chang, Chien-Yuan Lai, Cheng-Yuh Wu, Yi-Pin Lin, Wen-Wen Hsieh, Min-Shu Wang
  • Patent number: 11990477
    Abstract: In one embodiment, an integrated circuit cell includes a first circuit component and a second circuit component. The first circuit component includes fin field-effect transistors (finFETs) formed in a high fin portion of the integrated circuit cell, the high fin portion of the integrated circuit including a plurality of fin structures arranged in rows. The second circuit component that includes finFETs formed in a less fin portion of the integrated circuit cell, the less fin portion of the integrated circuit including a lesser number of fin structures than the high fin portion of the integrated circuit cell.
    Type: Grant
    Filed: September 24, 2020
    Date of Patent: May 21, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Wei-An Lai, Hui-Zhong Zhuang, Jiann-Tyng Tzeng, Wei-Cheng Lin, Lipen Yuan, Yan-Hao Chen
  • Patent number: 11990510
    Abstract: A semiconductor device, includes a channel region, and a source/drain region adjacent to the channel region. The source/drain region includes a first epitaxial layer, a second epitaxial layer epitaxially formed on the first epitaxial layer and a third epitaxial layer epitaxially formed on the second epitaxial layer, and the first epitaxial layer is made of SiAs.
    Type: Grant
    Filed: July 26, 2021
    Date of Patent: May 21, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Yi Peng, Ting Tsai, Chung-Wei Hung, Jung-Ting Chen, Ying-Hua Lai, Song-Bor Lee, Bor-Zen Tien
  • Publication number: 20240159878
    Abstract: A range detection device and a method for range detection thereof are disclosed. An optical sensing element receives a reflected signal of external light signal for triggering a transformation element to generate an electrical signal of receiving detection. Range detection data are generated to an operation processing unit according to the electrical signal of receiving detection and an electrical signal of reference. A plurality of first item data of the range detection data are compressed and operated to generate a plurality of first operation data to be stored as stored data. Further, the first item data correspond to a plurality of first storage addresses. The first operation data correspond to a plurality of second storage addresses. A first address amount of the first storage addresses is greater than a second address amount of the second storage addresses. Thereby, more storage addresses will be spared and hence extending the detection range.
    Type: Application
    Filed: November 14, 2023
    Publication date: May 16, 2024
    Inventor: Chih-Wei Lai
  • Publication number: 20240160828
    Abstract: A method of generating an IC layout diagram includes receiving an IC layout diagram including a gate region and a gate via, the gate via being positioned at a location within an active region and along a width of the gate region extending across the active region, receiving a first gate resistance value of the gate region, retrieving a second gate resistance value from a resistance value reference based on the location and the width, using the first and second resistance values to determine that the IC layout diagram does not comply with a design specification, and based on the non-compliance with the design specification, modifying the IC layout diagram.
    Type: Application
    Filed: January 24, 2024
    Publication date: May 16, 2024
    Inventors: Ke-Ying SU, Jon-Hsu HO, Ke-Wei SU, Liang-Yi CHEN, Wen-Hsing HSIEH, Wen-Koi LAI, Keng-Hua KUO, KuoPei LU, Lester CHANG, Ze-Ming WU
  • Patent number: 11982866
    Abstract: An optical element driving mechanism is provided and includes a fixed assembly, a movable assembly, a driving assembly and a stopping assembly. The fixed assembly has a main axis. The movable assembly is configured to connect an optical element, and the movable assembly is movable relative to the fixed assembly. The driving assembly is configured to drive the movable assembly to move relative to the fixed assembly. The stopping assembly is configured to limit the movement of the movable assembly relative to the fixed assembly within a range of motion.
    Type: Grant
    Filed: December 15, 2022
    Date of Patent: May 14, 2024
    Assignee: TDK TAIWAN CORP.
    Inventors: Chao-Chang Hu, Liang-Ting Ho, Chen-Er Hsu, Yi-Liang Chan, Fu-Lai Tseng, Fu-Yuan Wu, Chen-Chi Kuo, Ying-Jen Wang, Wei-Han Hsia, Yi-Hsin Tseng, Wen-Chang Lin, Chun-Chia Liao, Shou-Jen Liu, Chao-Chun Chang, Yi-Chieh Lin, Shang-Yu Hsu, Yu-Huai Liao, Shih-Wei Hung, Sin-Hong Lin, Kun-Shih Lin, Yu-Cheng Lin, Wen-Yen Huang, Wei-Jhe Shen, Chih-Shiang Wu, Sin-Jhong Song, Che-Hsiang Chiu, Sheng-Chang Lin
  • Publication number: 20240155845
    Abstract: A method of forming a ferroelectric random access memory (FeRAM) device includes: forming a layer stack over a substrate, where the layer stack includes alternating layers of a first dielectric material and a word line (WL) material; forming first trenches extending vertically through the layer stack; filling the first trenches, where filling the first trenches includes forming, in the first trenches, a ferroelectric material, a channel material over the ferroelectric material, and a second dielectric material over the channel material; after filling the first trenches, forming second trenches extending vertically through the layer stack, the second trenches being interleaved with the first trenches; and filling the second trenches, where filling the second trenches includes forming, in the second trenches, the ferroelectric material, the channel material over the ferroelectric material, and the second dielectric material over the channel material.
    Type: Application
    Filed: January 16, 2024
    Publication date: May 9, 2024
    Inventors: TsuChing Yang, Hung-Chang Sun, Kuo Chang Chiang, Sheng-Chih Lai, Yu-Wei Jiang
  • Publication number: 20240153823
    Abstract: A method includes depositing a high-k gate dielectric layer over and along sidewalls of a semiconductor fin. The method further includes depositing an n-type work function metal layer over the high-k gate dielectric layer and performing a passivation treatment on the high-k gate dielectric layer through the n-type work function metal layer. The passivation treatment comprises a remote plasma process. The method further includes depositing a fill metal over the n-type work function metal layer to form a metal gate stack over the high-k gate dielectric layer. The metal gate stack comprising the n-type work function metal layer and the fill metal.
    Type: Application
    Filed: January 18, 2024
    Publication date: May 9, 2024
    Inventors: Pei Ying Lai, Chia-Wei Hsu, Cheng-Hao Hou, Xiong-Fei Yu, Chi On Chui
  • Patent number: 11979613
    Abstract: Encoding methods and apparatuses include receiving input video data of a current block in a current picture and applying a Cross-Component Adaptive Loop Filter (CCALF) processing on the current block based on cross-component filter coefficients to refine chroma components of the current block according to luma sample values. The method further includes signaling two Adaptive Loop Filter (ALF) signal flags and two CCALF signal flags in an Adaptation Parameter Set (APS) with an APS parameter type equal to ALF or parsing two ALF signal flags and two CCALF signal flags from an APS with an APS parameter type equal to ALF, signaling or parsing one or more Picture Header (PH) CCALF syntax elements or Slice Header (SH) CCALF syntax elements, wherein both ALF and CCALF signaling are present either in a PH or SH, and encoding or decoding the current block in the current picture.
    Type: Grant
    Filed: June 28, 2022
    Date of Patent: May 7, 2024
    Assignee: HFI INNOVATION INC.
    Inventors: Ching-Yeh Chen, Olena Chubach, Chen-Yen Lai, Tzu-Der Chuang, Chih-Wei Hsu, Yu-Wen Huang
  • Publication number: 20240142546
    Abstract: Disclosed is a method for testing and evaluating a short-circuit withstand capability of a press-pack power component.
    Type: Application
    Filed: October 11, 2023
    Publication date: May 2, 2024
    Inventors: Hui LI, Renkuan LIU, Ran YAO, Wei LAI, Zeyu DUAN, Zheyan ZHU, Bailing ZHOU, Siyu CHEN, Jinyuan LI, Zhongyuan CHEN
  • Patent number: 11971601
    Abstract: An imaging lens assembly includes a plurality of optical elements and an accommodating assembly, wherein the accommodating assembly is for containing the optical elements. The accommodating assembly includes a conical-shaped light blocking sheet and a lens barrel. The conical-shaped light blocking sheet includes an out-side portion and a conical portion, and the conical portion is connected to the out-side portion. The conical portion includes a conical structure tapered from the out-side portion toward one of an object-side and an image-side along the optical axis. The lens barrel is disposed on one side of the conical portion. The optical elements include a most object-side optical element, a most image-side optical element and at least one optical element. The conical structure of the conical-shaped light blocking sheet is physically contacted with only one of the lens barrel, the most object-side optical element and the most image-side optical element.
    Type: Grant
    Filed: June 18, 2021
    Date of Patent: April 30, 2024
    Assignee: LARGAN PRECISION CO., LTD.
    Inventors: Yu-Chen Lai, Chih-Wei Cheng, Ming-Ta Chou, Ming-Shun Chang
  • Patent number: 11971038
    Abstract: A single-stage enthalpy enhancing rotary compressor and an air conditioner having same. The single-stage enthalpy enhancing rotary compressor includes: at least one single-stage cylinder, a rotator, an upper flange, and a lower flange. The rotator is arranged inside the cylinder and is rotatable, a compression chamber is formed between the rotator and an inner peripheral wall of the cylinder, a vapor injection opening is defined in at least one of the upper flange the lower flange, and the vapor injection opening is configured to supply gas outside the compressor to the compression chamber directly. According to the present disclosure, two-stage compression is realized without adding an extra cylinder, thereby effectively enhancing a circulation of refrigerant, improving cooling performance of the air conditioner under high environmental temperatures.
    Type: Grant
    Filed: September 26, 2022
    Date of Patent: April 30, 2024
    Assignee: GREE ELECTRIC APPLIANCES, INC. OF ZHUHAI
    Inventors: Guanghui Xia, Xiaocheng Lai, Shuo Xiong, Junchu Liang, Boming Zhu, Lihui Zhang, Wei Zhu, Xuechao Ding, Fuqiang Zhang, Hao Mei
  • Patent number: 11969448
    Abstract: A probiotic composition for improving an effect of a chemotherapeutic drug of Gemcitabine on inhibiting pancreatic cancer is disclosed in the present disclosure. The probiotic composition comprises an effective amount of Lactobacillus paracasei GMNL-133, an effective amount of Lactobacillus reuteri GMNL-89, and a pharmaceutically acceptable carrier, wherein the Lactobacillus paracasei GMNL-133 was deposited in the China Center for Type Culture Collection on Sep. 26, 2011 under an accession number CCTCC NO. M 2011331, and the Lactobacillus reuteri GMNL-89 was deposited in the China Center for Type Culture Collection on Nov. 19, 2007 under an accession number CCTCC NO. M 207154. A method for improving the effect of the chemotherapeutic drug of Gemcitabine on inhibiting pancreatic cancer is further disclosed in the present disclosure.
    Type: Grant
    Filed: May 12, 2021
    Date of Patent: April 30, 2024
    Assignee: GENMONT BIOTECH INC.
    Inventors: Wan-Hua Tsai, I-ling Hsu, Shan-ju Hsu, Wen-ling Yeh, Ming-shiou Jan, Wee-wei Chieng, Li-jin Hsu, Ying-chun Lai