Abstract: An image processing apparatus (10) capable of reducing the bandwidth and capacity required for a frame memory and preventing image quality degradation includes: a selecting unit (14) that selectively switches between first and second processing modes, a frame memory (12); a storing unit (11) that (i) down-samples an input image by deleting predetermined frequency information included in the input image and stores the input image as a down-sampled image in the frame memory (12) when the switching unit switches to the first processing mode, and (ii) stores the input image without down-sampling in the frame memory (12) when the switching unit switches to the second processing mode; and a reading unit (13) that (i) reads out the down-sampled image from the frame memory (12) and up-samples the down-sampled image when the switching unit switches to the first processing mode, and (ii) reads out the input image without down-sampling from the frame memory (12) when the switching unit switches to the second processing

Abstract: A method and apparatus to produce high-level synthesis Register Transfer Level designs utilises a trade-off between power dissipation and area usage in data path allocation. Power dissipation and area constraints and a priority between them are input. An algorithm automatically decides the number of registers that are to be used, according to the specified priority and constraints specified. Power management formulations can be used to gear the allocation process to trade lower power management costs for equivalent savings in register areas. Multi-criteria optimisation Integer Linear Programming is utilised with heuristically determined power and area weightings to suit different predefined requirements of the chip design. Bipartite weighted Assignment is used to determine the number of registers to be used at every stage, through cost formulations and the Hungarian Algorithm.

Abstract: A method and apparatus to produce high-level synthesis Register Transfer Level designs utilises a trade-off between power dissipation and area usage in data path allocation. Power dissipation and area constraints and a priority between them are input. An algorithm automatically decides the number of registers that are to be used, according to the specified priority and constraints specified. Power management formulations can be used to gear the allocation process to trade lower power management costs for equivalent savings in register areas. Multi-criteria optimisation Integer Linear Programming is utilised with heuristically determined power and area weightings to suit different predefined requirements of the chip design. Bipartite weighted Assignment is used to determine the number of registers to be used at every stage, through cost formulations and the Hungarian Algorithm.

Abstract: A method and apparatus for auto-generation of shift register file for high-level synthesis compiler includes parsing input source codes for specific definition of shift register file, a plurality of compiler directives to indicate the shift register file name, shift register file size, shift register file read access order, and shift register file write timing of the specific shift register file. The invention also includes determining the shifting interval of shift register file with specific definition after each reading or writing automatically. The invention further includes determining if the shift register file with specific definition has been generated, generating shift register file with specific definition if it has not been generated, and generating shift register file control signals to access the shift register file with specific definition.