Patents by Inventor Wei-Lien Yang
Wei-Lien Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9280509Abstract: In one embodiment, an apparatus may include a rising edge detector to detect a rising edge in a signal. The apparatus may also include a counter to perform a count to a first value based on an input clock signal. The apparatus may also include an output unit to generate a sleep signal after the first value is reached if the rising edge detector does not detect the rising edge in the signal.Type: GrantFiled: June 29, 2012Date of Patent: March 8, 2016Assignee: INTEL CORPORATIONInventor: Wei-Lien Yang
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Patent number: 9231753Abstract: In one embodiment, an apparatus including a phase detector unit to determine a phase difference between an inverted reference clock signal and a feedback clock signal. The apparatus further includes a controller unit to generate a delay signal based on the phase difference. The apparatus further includes a set of voltage-controlled delay lines to generate phase outputs based on the delay signal, where the phase outputs are provided by the apparatus to a clock generator unit to generate an oversampled clock signal for data recovery by a receiver.Type: GrantFiled: July 9, 2014Date of Patent: January 5, 2016Assignee: Intel CorporationInventor: Wei-Lien Yang
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Patent number: 9160585Abstract: In one embodiment, an apparatus may include a de-serializer to convert serial data to parallel data, and a counter to provide an update signal based on a bit count of the serial data. The apparatus may further include a synchronizer to provide a synchronization signal when a target clock signal is synchronized with the update signal. The apparatus may further include an output unit to provide a validation indicator in response to the synchronization signal.Type: GrantFiled: May 31, 2012Date of Patent: October 13, 2015Assignee: Intel CorporationInventor: Wei-Lien Yang
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Patent number: 9143314Abstract: In one embodiment, an apparatus including a phase detector unit to determine a phase difference between a reference clock signal and a feedback clock signal. The apparatus further includes a controller unit to generate a delay signal based on the phase difference. The apparatus further includes a set of voltage-controlled delay lines to generate phase outputs based on the delay signal, where the phase outputs are provided by the apparatus to a clock generator unit to generate an oversampled clock signal for data recovery by a receiver.Type: GrantFiled: June 11, 2014Date of Patent: September 22, 2015Assignee: Intel CorporationInventor: Wei-Lien Yang
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Patent number: 9130817Abstract: Described herein are an apparatus, system, and method for generating pulse modulated (PWM) signals. The apparatus (e.g., input-output transmitter) comprises: an edge detector to detect one of a rising or falling edges of a clock signal; a counter to count up or down in response to detecting one of the rising or falling edges of the clock signal, the counter to generate a select signal; and a control unit to receive a data signal for transmission to a receiver and to generate a PWM signal as output according to a value of the select signal and the data signal, wherein the receiver and the transmitter are a Mobile Industry Processor Interface (MIPIĀ®) M-PHYSM receiver and transmitter.Type: GrantFiled: December 15, 2011Date of Patent: September 8, 2015Assignee: Intel CorporationInventor: Wei-Lien Yang
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Publication number: 20140369400Abstract: In one embodiment, an apparatus including a phase detector unit to determine a phase difference between an inverted reference clock signal and a feedback clock signal. The apparatus further includes a controller unit to generate a delay signal based on the phase difference. The apparatus further includes a set of voltage-controlled delay lines to generate phase outputs based on the delay signal, where the phase outputs are provided by the apparatus to a clock generator unit to generate an oversampled clock signal for data recovery by a receiver.Type: ApplicationFiled: July 9, 2014Publication date: December 18, 2014Inventor: Wei-Lien Yang
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Patent number: 8890726Abstract: In one embodiment, an apparatus may include a clock generator to generate a first clock signal. The apparatus may also include a serializer to generate serial data based on a transmit clock signal and parallel input data. The apparatus may also include a signal generator to generate at least two differential signals based on the first clock signal and the serial data.Type: GrantFiled: February 17, 2014Date of Patent: November 18, 2014Assignee: Intel CorporationInventor: Wei-Lien Yang
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Publication number: 20140294060Abstract: In one embodiment, an apparatus including a phase detector unit to determine a phase difference between a reference clock signal and a feedback clock signal. The apparatus further includes a controller unit to generate a delay signal based on the phase difference. The apparatus further includes a set of voltage-controlled delay lines to generate phase outputs based on the delay signal, where the phase outputs are provided by the apparatus to a clock generator unit to generate an oversampled clock signal for data recovery by a receiver.Type: ApplicationFiled: June 11, 2014Publication date: October 2, 2014Inventor: Wei-Lien Yang
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Patent number: 8848850Abstract: Mechanisms and techniques to evaluate data for a high speed I/O receiver logic. In an embodiment, a receiver circuit shifts a bit into a shift circuit in response to a rising edge of a data signal, where a count is started in response to the bit being subsequently shifted out of the shift circuit. Based on a value of the count, the receiver circuit generates a control signal for preparing physical layer receiver logic to transition to a burst mode of operation. In another embodiment, a receiver circuit includes a frequency divider to operate based on a data signal and a clock signal, wherein, based on operation of the frequency counter, a control signal is generated to indicate a line reset for physical layer receiver logic. The receiver circuit provides a feedback signal, based on the control signal, which is to limit activation of the frequency divider.Type: GrantFiled: September 25, 2012Date of Patent: September 30, 2014Assignee: Intel CorporationInventor: Wei-Lien Yang
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Patent number: 8823432Abstract: In one embodiment, an apparatus may include a pulse generator to generate an oversampled clock signal. The apparatus may also include a sample and hold unit to provide at least two differential input signals based on the oversampled clock signal. The apparatus may further include a conversion unit to generate a single-ended signal based on the at least two differential input signals. The apparatus may also include a counter to determine a count of rising and falling edges of the single-ended signal based on the oversampled clock signal.Type: GrantFiled: December 27, 2013Date of Patent: September 2, 2014Assignee: Intel CorporationInventor: Wei-Lien Yang
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Patent number: 8816885Abstract: In one embodiment, an apparatus may include a de-serializer to convert serial data into two parallel data streams, and a control unit to provide a first update signal and a second update signal based on a bit count of the serial data. The apparatus may further include a target component having an input bus, the input bus including a first portion and a second portion. The apparatus may further include a first output unit to provide the first set of parallel data to the first portion of the input bus, and a second output unit to provide the second set of parallel data to the second portion of the input bus.Type: GrantFiled: June 29, 2012Date of Patent: August 26, 2014Assignee: Intel CorporationInventor: Wei-Lien Yang
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Publication number: 20140226708Abstract: Described herein are an apparatus, system, and method for generating pulse modulated (PWM) signals. The apparatus (e.g., input-output transmitter) comprises: an edge detector to detect one of a rising or falling edges of a clock signal; a counter to count up or down in response to detecting one of the rising or falling edges of the clock signal, the counter to generate a select signal; and a control unit to receive a data signal for transmission to a receiver and to generate a PWM signal as output according to a value of the select signal and the data signal, wherein the receiver and the transmitter are a Mobile Industry Processor Interface (MIPIĀ®) M-PHYSM receiver and transmitter.Type: ApplicationFiled: December 15, 2011Publication date: August 14, 2014Inventor: Wei-Lien Yang
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Patent number: 8797075Abstract: In one embodiment, an apparatus including a phase detector unit to determine a phase difference between an inverted reference clock signal and a feedback clock signal. The apparatus further includes a controller unit to generate a delay signal based on the phase difference. The apparatus further includes a set of voltage-controlled delay lines to generate phase outputs based on the delay signal, where the phase outputs are provided by the apparatus to a clock generator unit to generate an oversampled clock signal for data recovery by a receiver.Type: GrantFiled: June 25, 2012Date of Patent: August 5, 2014Assignee: Intel CorporationInventor: Wei-Lien Yang
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Publication number: 20140211894Abstract: In one embodiment, an apparatus may include a de-serializer to convert serial data to parallel data, and a counter to provide an update signal based on a bit count of the serial data. The apparatus may further include a synchronizer to provide a synchronization signal when a target clock signal is synchronized with the update signal. The apparatus may further include an output unit to provide a validation indicator in response to the synchronization signal.Type: ApplicationFiled: May 31, 2012Publication date: July 31, 2014Inventor: Wei-Lien Yang
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Patent number: 8779815Abstract: In one embodiment, an apparatus including a phase detector unit to determine a phase difference between a reference clock signal and a feedback clock signal. The apparatus further includes a controller unit to generate a delay signal based on the phase difference. The apparatus further includes a set of voltage-controlled delay lines to generate phase outputs based on the delay signal, where the phase outputs are provided by the apparatus to a clock generator unit to generate an oversampled clock signal for data recovery by a receiver.Type: GrantFiled: June 25, 2012Date of Patent: July 15, 2014Assignee: Intel CorporationInventor: Wei-Lien Yang
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Publication number: 20140159780Abstract: In one embodiment, an apparatus may include a clock generator to generate a first clock signal. The apparatus may also include a serializer to generate serial data based on a transmit clock signal and parallel input data. The apparatus may also include a signal generator to generate at least two differential signals based on the first clock signal and the serial data.Type: ApplicationFiled: February 17, 2014Publication date: June 12, 2014Inventor: Wei-Lien Yang
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Publication number: 20140103978Abstract: In one embodiment, an apparatus may include a pulse generator to generate an oversampled clock signal. The apparatus may also include a sample and hold unit to provide at least two differential input signals based on the oversampled clock signal. The apparatus may further include a conversion unit to generate a single-ended signal based on the at least two differential input signals. The apparatus may also include a counter to determine a count of rising and falling edges of the single-ended signal based on the oversampled clock signal.Type: ApplicationFiled: December 27, 2013Publication date: April 17, 2014Inventor: Wei-Lien Yang
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Patent number: 8692699Abstract: In one embodiment, an apparatus may include a clock generator to generate a format clock signal. The apparatus may also include a serializer to generate serial data based on a transmit clock signal and parallel input data. The apparatus may also include a signal generator to generate at least two differential signals based on the format clock signal and the serial data.Type: GrantFiled: July 10, 2012Date of Patent: April 8, 2014Assignee: Intel CorporationInventor: Wei-Lien Yang
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Publication number: 20140086363Abstract: Mechanisms and techniques to evaluate data for a high speed I/O receiver logic. In an embodiment, a receiver circuit shifts a bit into a shift circuit in response to a rising edge of a data signal, where a count is started in response to the bit being subsequently shifted out of the shift circuit. Based on a value of the count, the receiver circuit generates a control signal for preparing physical layer receiver logic to transition to a burst mode of operation. In another embodiment, a receiver circuit includes a frequency divider to operate based on a data signal and a clock signal, wherein, based on operation of the frequency counter, a control signal is generated to indicate a line reset for physical layer receiver logic. The receiver circuit provides a feedback signal, based on the control signal, which is to limit activation of the frequency divider.Type: ApplicationFiled: September 25, 2012Publication date: March 27, 2014Applicant: INTEL CORPORATIONInventor: Wei-Lien Yang
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Patent number: 8653868Abstract: In one embodiment, an apparatus may include a pulse generator to generate an oversampled clock signal. The apparatus may also include a sample and hold unit to provide at least two differential input signals based on the oversampled clock signal. The apparatus may further include a conversion unit to generate a single-ended signal based on the at least two differential input signals. The apparatus may also include a counter to determine a count of rising and falling edges of the single-ended signal based on the oversampled clock signal.Type: GrantFiled: June 28, 2012Date of Patent: February 18, 2014Assignee: Intel CorporationInventor: Wei-Lien Yang